Buck Regulator Research Articles

High efficiency DCM buck converter with dynamic logic based adaptive switch-time control

This paper presents a dynamic logic based adaptive switch-time control circuit (DASTC) for fast control to minimize body diode conduction losses and dead-time of a buck regulator operating in discontinuous conduction mode. Dead-time is an important metric for improving efficiency of low voltage converters. DASTC provides instant sensing and feedback based on the load to minimize dead-time significantly compared to prior-art and scales low side power switch pulse width adaptively across load currents, just enough to discharge the stored inductor energy fully. Furthermore, the converter has inherent pulse skipping mode to lower the switching frequency at light loads to enhance light load efficiency. The proposed 1.5 V buck regulator was fabricated in 0.35 $$\upmu$$μm CMOS process with an input voltage range of 1.8---3 V and load current range of 1---200 mA. Measurement results demonstrate a peak power efficiency of 94.6 % and a high overall power efficiency ( >~89 %) for load currents greater than 5 mA for $${V_{IN}}$$VIN = 1.8 V. The proposed scheme achieves 4× (~5 ns) better dead-time and 4---5.5 % better power efficiency compared to prior-art over the load current range.

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm2 by using 180 nm CMOS technology.

Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency

In CMOS switches, the input signal modulates the on-channel resistance for a constant gate voltage. This necessitates over design of CMOS switches. Also, further CMOS scaling in the nanometer regime has failed to improve energy efficiency due to increasing leakage energy. Looking beyond CMOS, nanoelectromechanical (NEM) relays are a promising class of emerging devices that exhibit energy-efficient switching and zero leakage operation. $R_{\rm on}$ of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite $R_{\rm off}$ offers significant area and power advantages over CMOS. Numerous end applications of NEM relay logic circuits have been proposed recently, including digital logic and memory. NEMS-based miniature switches form an interesting alternative in power management integrated circuits, the area of which is primarily dominated by CMOS power transistors. This study explores discontinuous-conduction mode buck regulator with specifications suitable for portable applications using a NEMS-CMOS hybrid design, and the results are compared against a standard commercial $0.35\hbox{-}{\rm \mu m}$ CMOS implementation. The electromechanical model has been developed for a suspended gate relay operating at 1 V with a nominal air gap of $5\hbox{--}10\; {\rm nm}$ published in the literature. The model accounts for the mechanical, electrical, and dispersion effects in the relay. This study shows that NEMS-CMOS hybrid dc–dc converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of $94.3\%$ at $100 \;{\rm mA}$ .

A Fast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator

An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ㎱, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 ㎒, an output voltage of 0.8 V, a maximum load current of 500 ㎃, and a peak efficiency of over 83%.

Driving circuit with high accuracy and large driving capability for high voltage buck regulators

This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators. A 40 V P-channel lateral double-diffused metal—oxide—semiconductor device whose drain—source and drain—gate can resist high voltage, but whose source—gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 μm CDMOS technology. From the results, compared with the accuracy of 16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover, power efficiency is up to 95% at 12 V input and 5 V output.

Pseudo-Type-III Compensation Integrated in a Voltage-Mode Buck Regulator

A pseudo-type-III compensation circuit integrated in a 2.25-MHz voltage-mode dc–dc buck regulator is presented. By summing high- and low-frequency signal paths at the outputs of an error amplifier, two zeros are generated to counteract the pair of complex $LC$ poles. Comparing with traditional and various reported type-III compensation, the proposed scheme is compact, and the area of the compensation capacitor is reduced by about 37%. The addition of a high-frequency path also helps to improve the transient response. Experimental results show that the fabricated regulator with the proposed scheme achieves good stability and fast load-step response. The output is settled within 10 $\mu \hbox{s}$ for a load current step of 400 mA. In addition, the measured load regulation and line regulation is 0.2%/A and 0.2%/V, respectively. The current consumption of the compensator is 120 $\mu \hbox{A}$ , and the measured maximum efficiency is up to 96%.

Half Load-Cycle Worked Dual Input Single Output DC/AC Inverter

A novel half load-cycle worked dual input single output (DISO) DC/AC inverter is presented. The basic circuit consists of a dual buck regulator, which works in continuous current mode. The working principle of DISO DC/AC inverter has been used. The control method applied for half load-cycle worked DISO DC/AC inverter has been studied. The control effects of the open-loop proportional control and closed-loop proportional-integral control are compared by using PSIM software. The parameters are adopted in the realistic simulation and experiment test. Moreover, the waveforms, such as voltage of modulation reference signal and output voltage, were given. The simulation and experiment results proved that the half load-cycle worked DISO DC/AC inverter could achieve good performance, gain a line frequency of 50 Hz, and verify the correctness of theoretical analysis.

Control of limit cycles in buck converters

Purpose – The purpose of this paper is to investigate limit cycles in digitally Proportional, Integral and Derivative (PID) controlled buck regulators. Filtering is examined as a means of removing the limit cycles in digitally controlled buck regulators. Design/methodology/approach – The paper explains why limit cycles occur in a digitally PID controlled buck converter. It then proceeds to propose two filters for their elimination. Results indicate the effectiveness of each of the filters. Findings – The paper gives a mathematical analysis of the occurrence of limit cycles in digitally controlled PID buck regulators. It finds that notch and comb filters are effective for the purpose of eliminating limit cycles in buck regulators. Originality/value – The paper employs a model of the buck regulator inclusive of the inductor loss – this was not done to date for this type of work. The paper analyses PID control. This was not done in the manner given. The paper addresses filtering as a means of removing limit cycles. It examines the effect of changing the digital controller parameters on the requirements of the filters.

Power Factor Correction for Three- Phase AC-AC Buck Regulator

Power Factor Correction for Three- Phase AC-AC Buck Regulator

Frequency compensation circuit for adaptive on‐time control buck regulator

A novel frequency compensation circuit for adaptive on-time control buck regulator is presented in this study, which mainly applied to provide power supply for double data rate synchronous dynamic random access memory system. Typical ripple control regulator possesses the advantage of fast transient response and unconditional stability. However, it suffers significant steady-state switching frequency variation when the input voltage and output voltage are varied. The on-time is directly proportional to the output voltage and inversely proportional to the input voltage so that the regulator can dynamically adjust the turn-on time of power switches according to the changes of input voltage and output voltage in steady-state operation by adaptive on-time control. Finally, an approximately fixed switching frequency is achieved. However, the variation of the switching frequency with load current still exists. Through the implementation of the frequency compensation circuit, the switching frequency variation caused by the load current variation can be effectively reduced in order to obtaining a more fixed switching frequency. The adaptive on-time control regulator with frequency compensation has been successfully fabricated with 0.35 µm 30 V complementary double-diffused metal oxide semiconductor process and full chip test results are provided to verify the proposed method in this study.

Parameters selection criteria of proportional–integral controller for a quadratic buck converter

A criteria for selection of parameters of proportional and integral (PI) controller for a DC–DC quadratic buck converter is proposed here. This procedure was developed from a large-signal model of converter in which a multiloop control scheme is added. This scheme has two control loops: an inner current loop, which improves the dynamic behaviour using a single gain, and a conventional PI controller as outer loop, which provides regulation. For the resulting system, the necessary conditions are derived for the existence of equilibrium point and stability in closed-loop. In comparison with the traditional method of loopshaping, which uses small-signal model, analytic expressions are found that simplifies the selection of controller parameters. At the end, the procedure is applied to 28 W quadratic buck regulator prototype and experimental results are given to verify the effectiveness.

Design of highly integrated power management unit with dual DVS-enabled regulators

A highly integrated power management unit (PMU) with dual DVS-enabled regulators is proposed in this paper. The PMU provides four buck regulators and two low dropout regulators, in which there are two DVS-enabled buck regulators. The output voltages can be optimized separately in the applications with two adaptive voltage domains. The PMU with dual DVS-enabled regulators provides high efficiency and convenient solution for portable devices. The voltage and current references are distributed by considering substrate noise from switching regulators. Interleaving operation of switching regulators minimizes input current ripple. Floating ground is generated in the control block of switching regulators by voltage buffer to further improve the negative power supply rejection (PSR?). The PMU is designed and fabricated with 0.13 μm CMOS process and occupies 5.29 mm2 active silicon area. Experimental results show that the PMU provides good isolation between channels and the DVS speeds for 250 mA ILoad are 63.6 and 45.5 μs/V when up-tracking and down-tracking, respectively. The proposed PMU can be embedded in low power SoCs, facilitating the DVFS scheme for multiple voltage domains.

Current Scheduling for Parallel Buck Regulated Battery Modules

In an electrical energy storage and delivery system, a parallel connection of battery modules can be used to increase the storage capability and power delivery demands. Parallel connection of batteries requires a robust battery management system as batteries may have different operating parameters such as state-of-charge (SoC), open-circuit voltage (OCV), internal resistance or battery chemistry. This paper focuses on current scheduling for a parallel connection of battery modules by utilizing buck regulators in the battery management system (BMS) of each module to improve the system performance via simultaneous, sequential and hybrid discharge scheduling algorithms. The results indicate the feasibility of the scheduling algorithms and motivate the use of parallel connected battery modules despite changes in battery operating parameters.

A NOVEL ARCHITECTURE OF MAXIMUM POWER POINT TRACKING FOR ULTRA-LOW-POWER BASED HYBRID ENERGY HARVESTER IN UBIQUITOUS DEVICES: A REVIEW

This research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome this limitation, the proposed ULP-HEH will use one power management unit with Maximum Power Point Tracking (MPPT) algorithm and impedance matching considerations to efficiently manage and combine power harvested from all three sources to achieve ULP consumptions. Among other crucial sub-modules of the ULP-HEH are its Asynchronous Finite State Machine (AFSM) cum resource sharing arbiter to prioritize and share energy sources for overall power reduction, an efficient rectification scheme for the piezoelectric input, an adaptive feedback for ULP conditioning, Zero-Current Switching (ZCS) for semi-lossless switching, a self-start circuit for low ambient startup, a Boost converter, a Buck regulator, a fuzzy-based micro-battery charger and a de-multiplexer to switch between harvesting or charging capabilities. All of which are implemented for maximum output extraction and minimal losses. This ULP-HEH will be developed in PSPICE software, Verilog coding under Mentor Graphics environment and later to be verified using Field Programmable Gate Array (FPGA) board before the final layout implementation in CMOS 0.13-µm process technology. This battery-less ULP-HEH is expected to deliver 3.0-5.0V of regulated voltage output from low ambient sources of 35 mV at startup. An efficiency of 90% with an output power of 650 µm is expected when all sources are summed. Also, this ULP-HEH is aimed at reducing power consumption to at least twice (

DC/AC Converter Based on Buck Regulator

The introduction of DC/AC converter based on buck regulator is firstly shown, and the analysis of the converters working principle is taken. The control method applied for DC/AC converter based on buck regulator is studied also. The control effect of the open-loop proportional-differential control and closed-loop proportional-integral control are compared by using PSIM software. The parameters adopted in the realistic simulation, waveforms such as voltage of modulation reference and load were given. The simulation results proved that adopting the DC/AC converter could achieve a good performance and can gain a line frequency as 50Hz and the correctness of theoretical analysis.

PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators

This paper introduces a new Pulse-Width Modulation (PWM) control scheme for buck regulators that combines phase chopping with frequency hopping to achieve spur-free operation while delivering low output noise floor with no subharmonics due to hopping. The proposed regulator hops between two, four, or eight switching frequencies, but chops their phases to fully eliminate spurs, even with only two frequencies. Peaking in the noise floor around the eliminated spurs is minimized by hopping as fast as every switching cycle, and by spacing the frequencies 0.5 MHz apart. This results in less than 1.7% drop in the regulator's efficiency and less than 4 mV increase in the voltage ripple. Implemented in standard 0.35- μm CMOS technology, the proposed regulator's area and power overhead beyond conventional single-switching-frequency design is only 8% and 3%, respectively. With a spur-free spectrum and low noise floor across all frequencies, the proposed architecture can serve as a low-noise regulator for powering noise-sensitive loads without post linear regulation or additional passive filtering. Moreover, spur-free operation facilitates its integration in mixed-signal systems on chip without interfering with sensitive circuits that share the same substrate or power rails. The proposed architecture is also a good candidate for implementing class-D amplifiers, as it preserves the control loop's linearity.

An Improved State Space Average Model of Buck DC-DC Converter with all of the System Uncertainties

In this paper a complete state-space average model for the buck switching regulators is presented. The presented model includes the most of the regulator’s parameters and uncertainties. In modeling, the load current is assumed to be unknown, and it is assumed that the inductor, capacitor, diode and regulator active switch are non ideal and they have a resistance in conduction condition. Some other non ideal effects look like voltage drop of conduction mode of the diode and active switch are also considered. This model can be used to design a precise and robust controller that can satisfy stability and performance conditions of the buck regulator. Also the effects of the boost parameters on the performance of the regulator can be shown easily with this model. After presenting the complete model, the buck converter Benchmark circuit is simulated in PSpice and its results are compared with our model simulation results in MATLAB. The results show the merit of our model.

Output switching noise spectral analysis and modeling in buck regulators

Useful closed-form equations for describing the spectrum of inherent steady-state switching noise at the output of buck regulators in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) of operation are derived. The formulas can be used by analog/RF designers to predict and account for power supply noise early in the design cycle regardless of the specific design details of the regulator itself, which can save significant development and debugging effort later in the design cycle. The theoretical formulas are verified by measuring the noise spectrum of a standard off-the-shelf buck regulator commonly used for mixed-signal SoCs and comparing these measurements to the predictions made by the proposed formulas.

Sliding-Mode Control of a Dc/Dc Postfilter for Ripple Reduction and Efficiency Improvement in POL Applications

This paper proposes an active postfilter based on two Buck converters, connected in parallel, operating in complementary interleaving. In such a configuration the ripple in the load current could be virtually eliminated to improve the power quality in comparison with classical Point-Of-Load (POL) regulators based on a single Buck converter. The postfilter is designed to isolate the load from the main Buck regulator, leading to the proposed three-converter structure named BuckPS. The correct operation of the postfilter is ensured by means of a sliding-mode controller. Finally, the proposed solution significantly reduces the current harmonics injected into the load, and at the same time, it improves the overall electrical efficiency. Such characteristics are demonstrated by means of analytical results and illustrated using numerical results.

Fast transient voltage-mode buck regulator applying ramp signal with a variable DC-offset scheme

A ramp signal with variable DC-offset (RSVDC) scheme implemented in a voltage-mode controlled buck voltage regulator is proposed. To enhance the response of the voltage-mode controlled buck regulator during the load transient, the variable DC-offset ramp signal is applied to drive the duty cycle full or zero, so that the output voltage can instantly respond with load change. The model, compensator and loop gain of the proposed buck regulator are derived and demonstrated. The transistor-level of the RSVDC circuit including the hysteretic comparator, oscillator and the output feedback voltage amplifier is also presented. The controller using the RSVDC scheme was implemented by the TSMC 0.35 m 2P4M process. The simulated and experimental results show that the transient response using the RSVDC scheme is about 10 s, when the load changes from 0.1 to 1 A under a 5 1.8 V voltage conversion. The test results validate the feasibility of the RSVDC control scheme in a buck voltage regulator to fulfil a simple structure, assured stability and fast transient response requirements.