Branch Prediction Schemes Research Articles

Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction

To address the balanced requirements of performance, power consumption, and area in embedded systems, this paper introduces a 32-bit out-of-order processor based on the RISC-V instruction set, and the processor supports interrupt handling. This processor is designed to support the RV32IMC instruction subset and utilizes a four-stage pipeline structure featuring sequential instruction fetching, out-of-order execution, and out-of-order write-back. The main contributions are as follows:1) The segmented exclusive or G-share branch prediction scheme for embedded processors is proposed, which provides high branch prediction accuracy when the capacity of pattern history table (PHT) is small. 2) The work undertaken by hardware and software during interrupt response is reasonably divided, which allows for fast interrupt response with minimal resource consumption. Furthermore, the interrupt response time in vectored mode is reduced by simultaneously stacking the control and status registers (CSRs) and obtaining the interrupt service routine (ISR) entry address. Executing branch prediction-related programs within an identical environment, the processor detailed in this paper demonstrates an average prediction accuracy improvement of 1.2 % over G-share and 0.6 % over bi-mode branch prediction when employing the segmented exclusive or G-share branch prediction scheme. Building on this foundation, the on-chip debugging system and memory management unit have been implemented. The processor reaches 1.389 Dhrystone/MHz and 2.802 Coremark/MHz.

Modified Architecture of Tomasulo’s Algorithm using Adaptive Branch Predictor

This paper proposes modified architecture to implement the Tomasulo’s Algorithm using Adaptive branch prediction scheme, which evaluate the branch outcome by taking both local and global history dynamically. The choice of local vs. global branch prediction is made dynamically on a path based predictor that decides which branch must be taken on past correctness of choice.

A Hybrid Branch Prediction Approach For High-Performance Processors

Background: In a parallel processor, the pipeline cannot fetch the conditional instructions with the next clock cycle, leading to a pipeline stall. Therefore, conditional instructions create a problem in the pipeline because the proper path can only be known after the branch execution. To accurately predict branches, a significant predictor is proposed for the prediction of the conditional branch instruction. Method: In this paper, a single branch prediction and a correlation branch prediction scheme are applied to the different trace files by using the concept of saturating counters. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes. Results: Firstly, a single branch prediction and correlation branch prediction technique are applied to the trace files using saturating counters. By comparison, it can be observed that a correlation branch prediction technique provides better results by enhancing the accuracy rate of 2.25% than the simple branch prediction. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes. The results suggest that the proposed hybrid branch prediction schemes provide an increased accuracy rate of 3.68% and 1.43% than single branch prediction and correlation branch prediction. Conclusion: The proposed hybrid branch prediction scheme gives a lower misprediction rate and higher accuracy rate than the simple branch prediction scheme and correlation branch prediction scheme.

Implementation and comparison of bi-modal dynamic branch prediction with static branch prediction schemes

In a parallel processor, the pipeline cannot fetch the conditional instructions with the next clock cycle, leading to a pipeline stall. So, conditional instructions create a problem in the pipeline because the proper path can only be known after the branch execution. To accurately predict branches, a significant predictor is proposed for the prediction of the conditional branch instruction. Firstly, the always taken prediction scheme and always not-taken prediction scheme are applied to the trace files using a static branch prediction scheme. Further, a bi-modal dynamic branch prediction scheme is proposed, which uses the saturating counter to provide more accuracy rate than the other prediction schemes. The result suggests that the proposed bi-modal dynamic branch prediction scheme provides a higher accuracy rate than always taken and always not-taken static branch prediction by the rate of 9.82% and 6.12%, respectively. Moreover, the proposed bi-modal dynamic branch prediction limits the misprediction rate by 10.33% and 8.16% compared with the always taken and always not-taken static branch prediction scheme.

Selective branch prediction schemes based on FPGA MIPS processor for educational purposes

Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in order to predict both the direction of instructions execution and the address of the instruction to be executed next. In this paper, a design for a dynamic branch predictor was implemented in VHDL (VHSIC Hardware Description Language) then it was integrated with FPGA (Field Programmable Gate Arrays) MIPS (Microprocessor without Interlocked Pipelined Stages) processor and its ability to increase prediction accuracy and MIPS processor performance was approved. This predictor combines gshare and bimodal branch prediction techniques by dividing the PHT (Pattern History Table) into two branch streams corresponding to taken and not-taken states. This combined branch predictor was synthesized using the XILINX ISE (Integrated Software Environment) Design Suite 14.7 tool.

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

Branch prediction accuracy becomes more crucial in high-performance embedded processors. The importance of branch prediction in embedded processors continues to grow in the future. Many branch predictors have been proposed to alleviate the performance penalty due to branch mispredictions. However, recent embedded processors still have problems in increasing the branch prediction accuracy. This paper proposes number of taken branch instructions (NTB) branch predictor, a new dynamic branch predictor for high-performance embedded processors. The NTB branch predictor utilizes two-bit saturating counters in the pattern history table based on the information about the number of taken-branches in the global branch history. The proposed NTB branch predictor achieves improved accuracy by making use of longer branch history with no hardware overhead, because hardware resources for the proposed NTB branch predictor are independent of the history length. By contrast, existing dynamic branch prediction schemes require more hardware resources as the history length increases. According to our experiments with a 4 KB branch predictor which suits embedded processors, the NTB branch predictor improves the prediction accuracy by 7.11 and 43.41 % on average over the perceptron predictor and the two-level adaptive branch predictor, respectively.

Modified Architectural Support to Implement Tomasulo’s Algorithm on Tournament Branch Predictor

This paper proposes modified architecture of 21264, Out-Of-Order, six-way issue microprocessor. The proposed modified architecture implements Tomasulo's algorithm using tournament branch prediction scheme to improve the performance of processor. Tomasulo's Algorithm controls the operation of the Common Data Bus (CDB) by means of tag mechanism. A tag is a 4-bit number used to identify separately each of eleven sources which can feed the CDB. The proposed modified architecture will evaluate branch outcome by taking both local and global history. The choice of global-versus-local branch prediction is made dynamically on a path-based predictor that decides which predictor to use, based on the past correctness of choice.

The Impact of Speculative Execution on SMT Processors

By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due to incorrect control speculations, a significant number of these in-flight instructions are discarded from the pipelines of SMT processors (which is a direct consequence of these pipelines getting wider and deeper). Although increasing the accuracy of branch predictors may reduce the number of instructions so discarded from the pipelines, the prediction accuracy cannot be easily scaled up since aggressive branch prediction schemes strongly depend on the particular predictability inherently to the application programs. In this paper, we present an efficient thread scheduling mechanism for SMT processors, called SAFE-T (Speculation-Aware Front-End Throttling): it is easy to implement and allows an SMT processor to selectively perform speculative execution of threads according to the confidence level on branch predictions, hence preventing wrong-path instructions from being fetched. SAFE-T provides an average reduction of 57.9% in the number of discarded instructions and improves the instructions per cycle (IPC) performance by 14.7% on average over the ICOUNT policy across the multi-programmed workloads we simulate.

Dynamic branch prediction and control speculation

Branch prediction schemes have become an integral part of today's superscalar processors. They are one of the key issues in enhancing the performance of processors. Pipeline stalls due to conditional branches are one of the most significant impediments to realise the performance potential of superscalar processors. Many schemes for branch prediction that can effectively and accurately predict the outcome of branch instructions have been proposed. In this paper, an overview of some dynamic branch prediction schemes for superscalar processors are presented.

Clustered indexing for branch predictors

As a result of resource limitations, state in branch predictors is frequently shared between uncorrelated branches. This interference can significantly limit prediction accuracy. In current predictor designs, the branches sharing prediction information are determined by their branch addresses and thus branch groups are arbitrarily chosen during compilation. This feasibility study explores a more analytic and systematic approach to classify branches into clusters with similar behavioral characteristics. We present several ways to incorporate this cluster information as an additional information source in branch predictors. Our profile-based results demonstrate that cluster information is useful in various branch prediction schemes. When clustered indexing is applied, the same performance can be obtained with 2–8 times less hardware budget. For small predictor budgets, clustered indexing is very cost-effective, e.g., the misprediction rate in an 8 Kib gshare is reduced 12.3% on average for SPEC CPU2000 INT. For large budgets up to 4 Mib, clustered indexing reduces the number of mispredictions by 3–5%, or stated otherwise only half the hardware budget is required to obtain the same performance as the original gshare scheme.

Modeling Control Speculation for Timing Analysis

The schedulability analysis of real-time embedded systems requires worst case execution time (WCET) analysis for the individual tasks. Bounding WCET involves not only language-level program path analysis, but also modeling the performance impact of complex micro-architectural features present in modern processors. In this paper, we statically analyze the execution time of embedded software on processors with speculative execution. The speculation of conditional branch outcomes (branch prediction) significantly improves a program's execution time. Thus, accurate modeling of control speculation is important for calculating tight WCET estimates. We present a parameterized framework to model the different branch prediction schemes. We further consider the complex interaction between speculative execution and instruction cache performance, that is, the fact that speculatively executed blocks can generate additional cache hits/misses. We extend our modeling to capture this effect of branch prediction on cache performance. Starting with the control flow graph of a program, our technique uses integer linear programming to estimate the program's WCET. The accuracy of our method is demonstrated by tight estimates obtained on realistic benchmarks.

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations, matching the low-power characteristics of the target VLIW processors. Experimental results have been carried out on Lx, an industrial 4-issue VLIW architecture.

An alternative to branch prediction

Through this paper we developed an alternative approach to the present -- day two level dynamic branch prediction structures. Instead of predicting branches based on history information, we propose to pre - calculate the branch outcome. A pre - calculated branch prediction (PCB) determines the outcome of a branch as soon as all of the branch's operands are known. The instruction that produced the last branch's operand will trigger a supplementary branch condition estimation and, after this operation, it correspondingly computes the branch outcome. This outcome is cached into prediction table. The new proposed PCB algorithm clearly outperforms all the classical branch prediction schemes, simulations on SPEC and Stanford HSA benchmarks, proving to be very efficient. Also, our investigations related to architectural complexity and timing costs are quite optimistic, involving an original alternative to the present-day in branch prediction approach.

Branch prediction using both global and local branch history information

As the pipeline depth and issue rate of high-performance superscalar processors increase, the importance of an excellent branch predictor becomes more crucial to delivering the potential performance of a wide-issue, deep pipelined processor. Conventional two-level branch predictors predict the outcome of a branch either based on the local branch history information, comprising the previous outcomes of a single branch, or based on the global branch history information, comprising the previous outcomes of all branches. The authors propose a new branch prediction scheme, called LGshare, which employs both the global and local branch history information simultaneously to improve the branch prediction accuracy for superscalar processors. It is shown that LGshare can achieve higher branch prediction accuracy than conventional two-level predictors when the size of the pattern history table is fixed.

S/390 microprocessor design

The technical, business, and market requirements for large enterprise servers (mainframes) strongly influence the design of microprocessors for these systems. Specific characteristics of the ESA/390 and z/Architecture instruction set architectures lead to different pipeline and branch prediction strategies than are found in most other microprocessors. The requirements for robust, scalable performance across a wide range of workloads, highly efficient logical partitioning, and very high hardware reliability affect the cache structure, internal code, and hardware fault detection and recovery designs.

Trace Driven Simulation of Dynamic Branch Prediction Schemes

Simulation studies of two branch prediction schemes in superscalar pipelined computers are presented in this paper. The two studied meth ods are the Per-address Adaptive (PA) scheme and the Global Adaptive (GA) scheme. In addi tion, simulation studies of a modification of the PA scheme, called Switched P/G Adaptive (SPGA), are also presented. Using several benchmarks, it has been illustrated that SPGA scheme has promising results at the possible expense of slight hardware addition.

The block-based trace cache

The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-based trace cache implementation that can achieve higher IPC performance with more efficient storage of traces. Instead of explicitly storing instructions of a trace, pointers to blocks constituting a trace are stored in a much smaller trace table. The block-based trace cache renames fetch addresses at the basic block level and stores aligned blocks in a block cache. Traces are constructed by accessing the replicated block cache using block pointers from the trace table. Performance potential of the block-based trace cache is quantified and compared with perfect branch prediction and perfect fetch schemes. Comparing to the conventional trace cache, the block-based design can achieve higher IPC, with less impact on cycle time. Results: Using the SPECint95 benchmarks, a 16-wide realistic design of a block-based trace cache can improve performance 75% over a baseline design and to within 7% of a baseline design with perfect branch prediction. With idealized trace prediction, it is shown the block-based trace cache with an 1K-entry block cache achieves the same performance of the conventional trace cache with 32K entries.

Implementation and analysis of path history in dynamic branch prediction schemes

Accurate branch prediction is essential for providing higher performance levels in modern processors. Many branch predictors use branch execution history to identify repetitive branch behavior. Path history provides additional information that may help separate sequences of different branch instructions with identical execution history. We present a method to implement path history in hardware-based branch prediction, and a comprehensive simulation study of branch prediction strategies that integrate path history.

Target prediction for indirect jumps

As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be thrown away in the event of a branch misprediction, wide-issue, deeply pipelined processors must employ accurate branch predictors to effectively exploit their performance potential. Many existing branch prediction schemes are capable of accurately predicting the direction of conditional branches. However, these schemes are ineffective in predicting the targets of indirect jumps achieving, on average, a prediction accuracy rate of 51.8% for the SPECint95 benchmarks. In this paper, we propose a new prediction mechanism, the target cache, for predicting indirect jump targets. For the perl and gcc benchmarks, this mechanism reduces the indirect jump misprediction rate by 93.4% and 63.35% and the overall execution time by 14% and 5%.