Bottom Wafer Research Articles

Wafer-scale silicon microfabrication technology toward realization of low-cost sub-THz waveguide devices

This paper presents a wafer-scale silicon microfabrication technology for the sub-terahertz (sub-THz) waveguide device mass production. Based on the effective scheme, a WR-5 (140–220 GHz) straight rectangular waveguide and a WR-2.8 (260–400 GHz) rectangular waveguide bandpass filter are implemented as demonstrated examples. The silicon deep reactive ion etching (DRIE) process is employed to etch through the total thickness of the silicon wafer and form the main waveguide channels. Then, a low-temperature thermal compression process is used to bond the trough-etched wafer with the top and bottom metallised silicon wafers to form the closed waveguide structures without any precise alignment process. The fabricated waveguide has the benefit of low transmission loss (0.03–0.05 dB mm−1) at the whole G band. Besides, to measure the fabricated WR-2.8 waveguide filter and solve the measuring equipment standard waveguide difference, silicon micromachined waveguide transitions are explored and fabricated to match two different frequency-band modules for measuring the waveguide filters in the desired full frequency band, which also has a potential application for the different size waveguide conversion. The measured results agree well with the simulated ones. The measured 3 dB bandwidth is 9.3%, with a central frequency of 343 GHz; the average insertion loss (IL) is about 1.6 dB in the pass band, including two extra straight waveguides of 8 mm length on input/output ends and two external waveguide-to-waveguide transitions. The proposed method provides a feasible and cost-effective solution for the mass production of high-performance waveguide devices and integrated systems in sub-THz frequency bands and beyond.

Process and Design Challenges for Hybrid Bonding

Hybrid bonding is one of the key technology to enable solutions for high bandwidth with increasing power and signal integrity. Hybrid bonding involves, face-to-face interconnect formation between wafers and it acts as an extension of fusion bonding technology. Wherein, dielectric materials such as silicon dioxide bond at room temperature and the copper vias embedded in the dielectric expand to form the electrical connections, enabling the interconnect formation between the top and bottom wafer.Hybrid bonding provides advantages over traditional C4 flip-chip bonding involving solder-based micro-bumps, such as, interconnect pitch scaling to less than 10 µm thereby providing higher interconnect density and increased power and signal speed efficiency for memory and high-performance computing application along with better reliability. It is compatible with standard CMOS fabrication technology.In this work, we would like to present the design and process challenges which may lead to improved bonding yield. To enable hybrid bonding with high yield it is necessary that the bonding surfaces are flat with low roughness. The optimized chemical mechanical polishing (CMP) process is one of the key process technology which enables surface topography to be less than 10 nm and surface roughness to be less than 0.8 nm. The surface topography is dependent on the metal via layout, interconnect density and the surrounding dielectrics and hence, these design parameters act as a guiding principle for the application-oriented definition of the design to accommodate different pitch sizes of interconnecting vias (from 1 µm to 10 µm). The mechanical properties of the materials play a key role as well as this will define the removal rate of dielectric and the metals during the CMP process which will affect the dishing and the surface topography. To achieve high bonding yield the surface topography is key as this will affect the bond front propagation and hence the bonded and non-bonded region between the dielectrics. To further improve the bonding yield we have applied a tailored annealing recipe which improves the bonding yield significantly. This paper would focus our work on topography improvement and overall bonding yield in detail and a comparison of bonding yield with and without dummy vias. Dummy vias in this context refer to the copper via structures that are not intended for interconnect formation but are there for CMP process optimization to achieve better process control. Hence, the dummy vias are not connected to the underlying routing metal layer.Figure 1, shows an ideal surface that would result in W2W bonding with high yield. Figure 2 shows, the defects such as high copper dishing, copper protrusion, dielectric erosion and poor surface topography which will result in poor bonding yield. Figure 3 shows the bonding using SiON as the bonding dielectric with (a) without dummy copper vias (~98% bond yield) and (b) with dummy copper vias (~88% bond yield). Figure 1

(Invited) Physical Analysis and Modeling of Wafer-to-Wafer Copper Hybrid Bonding at Sub-Micron Pitches

The bonding process has four sequential steps: plasma surface treatment, rinsing, bonding, and annealing. It is important to understand the details of all these steps to enable high performance bonding at sub-micron pitches. A multi-level back-end-of-line test vehicles at 1um and 0.5um pitches have been produced to evaluate the execution of the Tokyo Electron wafer-to-wafer (W2W) bonding tool platform. Subsequently several simulation and modeling approaches have been developed to better comprehend the impacts of different process conditions on the physical hybrid bonding results.Figure 1 shows the scanning electron microscope (SEM) image of the 1um bonding pad pitch Kelvin-via test structure that was successfully bonded and electrically tested. A median resistance of 0.44Ω has been measured for well-aligned 1um pitch kelvin-via measurements. Multiple variations of the test structures purposefully shift the top and bottom wafer patterning up to 100% mis-aligned to study the impact on electrical results from the bonding alignment. The corresponding electrical resistance, leakage and yield results provide statistically relevant feedback to improve the design and process integration of the test vehicle and W2W bonding platform.Maintaining a proper composition of the copper bond pads during plasma activation is necessary, especially if a lower anneal temperature post bond is desired. At low thermal budget bonding the oxides are not able to diffuse through any thick layer of modified copper formed between the pads during bonding which can significantly impede the electrical properties of the contact. The impact of plasma gas composition on the formation of surface copper species was determined using X-Ray Photoelectron Spectroscopy. For low temperature bonding, a simultaneous O2/H2 plasma treatment produces the thinnest copper oxide with the lowest theoretical resistivity. The activation gas chosen is based on the dielectric being used, but it has a significant impact on copper oxidation.If the bonding dielectric material is SiCN, then an O2 or O2/H2 mixed gas is best used for the activation process. The Cu2O content is less than the diffusion length for low temperature bonding for both gases, but the concentration of both CuO and Cu(OH)2 is high for the O2 treatment. At these concentrations, a low temperature O2 activation would create a copper contact with significant resistance. These results will help develop a plasma treatment to achieve good electrical contacts between hybrid bonded wafers with low thermal budget.A quantum chemistry simulation was developed to study how O/N-radicals modify the surface of SiO2 to increase the bond density. O atoms binding with H, N and C in the SiO2 films to create OH, CH2O, CO, HNO and nitic oxides (NO) groups. NO-groups are hydrolyzed to form additional surface OH during the rinsing step, increasing the density of Si-O-Si formation and total bonding energy. Atomistic molecular dynamic simulation also confirmed how nitrogen atoms introduce silanol and siloxane group to the surface during the surface activation treatment and the hydration reaction. The population effects of N atoms on bond formation were also studied, which indicated when more N atoms exist it will lead to improved bonding.Several plasma conditions were tested for the surface activation process to bond thermal silicon dioxide (TOX) to each other, and the bonding strength was calculated by the Maszara-Method after the annealing process. Comparing the bonding strength between TOX/TOX bond with N2 and O2 plasma under the same plasma conditions, the bonding strength using N2 plasma treatment is 1.7 times stronger than the bonding strength using O2 plasma treatment, indicating that the N2 plasma treatment is superior to the O2 plasma treatment.Finally, a multi-physics finite element model to simulate the post-bond distortion resulting from the wafer-to-wafer bonding process in room conditions was evaluated. The axisymmetric simulation model includes both the solid mechanics of the silicon wafers and the fluid mechanics of the air gap to accurately simulate the bond propagation dynamics. The two wafers, which may be warped by stressed films in preceding process steps, are initially separated at a small, fixed gap. As the center of upper wafer is pushed down by a striker, an adhesion model like Lennard-Jones potential simulates the contact propagation behavior between the two wafers. The simulation also includes other bonder process parameters and hardware designs to provide accurate distortion results. The outputs of the simulation are validated against a numerical model. The simulation model is also validated against direct wafer bonding experiment results. Figure 1

From dissolution to controlled macrostepping of 4H-SiC during liquid Si-induced structuring in a sandwich configuration

The structuring of Si face 4°off 4H-SiC surfaces was investigated using Si melting in a SiC/Si/SiC sandwich configuration. The stacks were treated at 1550–1600 °C under H2 in a RF-heated cold-wall reactor. By fixing the liquid Si thickness to 30 µm, the vertical thermal gradient inside the stack generates carbon transport from the bottom to the top SiC wafer. The constant dissolution of the bottom SiC wafer (1.7 µm/h at 1550 °C) leads to surface structuring in macrosteps. The regularity of these macrosteps can be reproducibly controlled when performing the process on an epitaxial layer thanks to the pre-structuration in parallel microsteps of such kind of surfaces. The best regularity of the steps was obtained after a structuring process of 2 h, with an average terrace width of ∼3–5 µm.

Transport Phenomena during Liquid Si-Induced 4H-SiC Surface Structuring in a Sandwich Configuration

4H-SiC/Si(liq)/4H-SiC stacks were treated at 1550-1600°C under H2 in a RF-heated cold-wall reactor in order to generate macrosteps-structuring of the 4°off SiC(0001) wafers. Using 400 μm thick liquid Si, the observed important matter transport from the edges to the center of the same wafer was attributed to RF-induced convection rolls inside the thick liquid Si. When the liquid thickness was reduced down to 30 μm, the matter transport followed this time the vertical thermal gradient like in the case of liquid phase epitaxy. The dissolution rate of the bottom (hotter) wafer was found to increase from 1.7 μm/h at 1550°C to 3.3 μm/h at 1600°C. The use of H2 gas was found essential to the system since it does not generate gas trapping (unlike Ar) and it participates to the creation of the vertical thermal gradient.

3D Heterogenous Integrated Wideband Switchable Bandpass Filter Bank for Millimeter Wave Applications

This article proposes a three-dimensional heterogenous-integrated (3DHI) switchable bandpass filter bank with two independent wideband filter channels that cover 26–40 GHz and 32.5–40 GHz, respectively. An accurate wafer-level process with a high hollowed ratio of the applied 8-inch high-resistivity-silicon (HR-Si) interposer wafers is presented to form both compact filter channels. Above the interdigital filter patterns fabricated on the bottom interposer wafer, deep cavities are etched in the cap interposer wafer to improve the quality factor of the filter bank. Besides the cavities, the cap interposer wafer is 35% hollow inside, which two bare dies of GaAs single-pole double-throw (SPDT) switches and two thin film resistors are attached to the bottom interposer after the wafer-to-wafer (W2W) bonding. To ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. Measurement results show that the switchable filter bank achieves a high isolation of 50 dB and a competitive shape factor (BW30dB/BW3dB) of about 1.3. In addition, the size of the switchable filter bank is only 7.0 mm × 3.5 mm × 0.6 mm, and the weight is only 0.1 g.

Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication

We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the dicing process on the warpage reduction and the thermal stress of bonded wafer are investigated by varying the dicing pitch from a one pitch as chip size to a quarter pitch. When the dicing pitch decreases to a quarter pitch, the bonded wafer warpage is observed to decrease by 27.8%. A full wafer model is established with the representative volume element (RVE) method in simulation and validated by good agreement with the measured wafer warpage data. The radial stress distribution of bonded wafer indicates tensile stress for the dynamic random access memory (DRAM) layers and compressive stress for the DRAM/Si substrate interface of top and bottom wafers due to the shrinkage of the DRAM layers under the temperature decrease from its high fabrication temperature to the room temperature. The radial stress distribution after the dicing process with different pitches indicates a similar stress level after one-pitch dicing and half-pitch dicing. When the dicing pitch decreases to a quarter value, the compressive stress decreases, correspondingly resulting in a warpage reduction. The stress released by interrupting the continuity of the wafer with a small dicing pitch is revealed to be the origin of wafer warpage reduction. This study provides a guideline of dicing street pitch for warpage reduction and is useful for optimizing the device layout design.

(Invited) Optoelectronic and 3D Applications with Die to Wafer Direct Bonding: From Mechanisms to Applications

—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.IntroductionSOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology available in many industrial microelectronic factories. Direct bonding of 200 mm or 300 mm silicon wafers are nowadays well mastered. For many innovative applications, it could be interesting to introduce new materials like InP, AsGa, GaN on a silicon platform. Heterostructure bonding then needs to be developed. This could be done with wafer-to-wafer bonding. However, wafers made of these new materials usually have diameters much smaller than that of silicon wafers, especially if CMOS are required on the silicon wafers. Indeed, advanced CMOS devices are nowadays only available on 200/300 mm silicon wafers. Even if the bonding of a small wafer on a bigger one is easily feasible, the silicon surface lost will be detrimental to the cost of the device. Moreover, usually, a very small surface of the new material is needed on the silicon wafer. With a wafer-to-wafer bonding (W2W), the new material surface loss will be quite important. Die-to-wafer (D2W) bonding is thus the solution to both issues in order to put only a small amount of new material where it is needed and populate all the active area on silicon wafers.D2W is also interesting in hybrid bonding with silicon wafers. Indeed, D2W enlarges design rules to mix different technologies (material, dies size) on the same bottom wafer while enabling high density of copper interconnects.. Hybrid D2W is then foreseen as being the next step for hybrid bonding in order to widen its application field.ResultsStarting with the well know fundamental mechanisms of silicon dioxide bonding [1] as well as copper and hybrid surface bonding [2], D2W bonding behavior will be discussed. Some specific features indeed have to be taken into account for die bonding. For instance, all the edge effects, during and after the bonding or the annealing, have a great impact on the bonding energy as well as on the interface defectivity. Moreover, specific bonding techniques using for instance liquid water films can be used only in D2W bonding. If these specific features are under control, very innovative structures can be obtained. It is possible for instance to bond small 3mm*3mm InP dies onto 200mm silicon photonic wafers as shown in Fig.1a [3]. Moreover, hybrid bonding interfaces can also be obtained between 6mm*4mm dies and a 300mm wafer as shown in Fig.1b. Obviously, alignment in mandatory during hybrid bonding. This can be obtained thanks to a die to wafer bonder. However, innovative technologies such as capillary assisted self-assembly can also be really interesting [4 -7]. The electrical characterization of the D2W hybrid bonding connection will be also discussed, showing roughly the same good results as for W2W hybrid bonding.AcknowledgmentThis work was funded thanks to the French National program “Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05.References 1 F. Fournel, et al., ECS J. Solid State Sci. Technol. 4, P124 (2015). 2 L.D. Cioccio, et al., J. Electrochem. Soc. 158, P81 (2011). 3 B. Szelag et al., Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform, IEEE J. Sel. Top. Quantum Electron., In Press (2019). 4 A. Jouve, et al., ECTC (2019). 5 T. Fukushima, et al., in 2011 IEEE 61st Electron. Compon. Technol. Conf. ECTC (2011), pp. 2050–2055. 6 E. Bourjot, et al., ECTC(2021) Figure 1

Quantum dot-integrated GaN light-emitting diodes with resolution beyond the retinal limit

Near-eye display technology is a rapidly growing field owing to the recent emergence of augmented and mixed reality. Ultrafast response time, high resolution, high luminance, and a dynamic range for outdoor use are all important for non-pixelated, pupil-forming optics. The current mainstream technologies using liquid crystals and organic materials cannot satisfy all these conditions. Thus, finely patterned light-emissive solid-state devices with integrated circuits are often proposed to meet these requirements. In this study, we integrated several advanced technologies to design a prototype microscale light-emitting diode (LED) arrays using quantum dot (QD)-based color conversion. Wafer-scale epilayer transfer and the bond-before-pattern technique were used to directly integrate 5-µm-scale GaN LED arrays on a foreign silicon substrate. Notably, the lithography-level alignment with the bottom wafer opens up the possibility for ultrafast operation with circuit integration. Spectrally pure color conversion and solvent-free QD patterning were also achieved using an elastomeric topographical mask. Self-assembled monolayers were applied to selectively alter the surface wettability for a completely dry process. The final emissive-type LED array integrating QD, GaN, and silicon technology resulted in a 1270 PPI resolution that is far beyond the retinal limit.

Numerical and experimental investigation on mc-Silicon growth process by varying the Si3N4 coating thickness of crucible

In the present work, the bottom-opening directional solidification technique was adopted to grow multi-crystalline silicon ingot. By varying the thickness of Si3N4 coating on the quartz crucible, the variation in carbon and oxygen concentration in the ingot has been analyzed. The axis-symmetric time-dependent 2D modeling has been done to analyze heat and mass transfer within the directional solidification furnace. We have analyzed the concentration of carbon monoxide, silicon oxide, silicon carbide, carbon and oxygen in the grown mc-Si ingots by varying the Si3N4 thickness. The oxygen and carbon impurities concentration are higher for the Si3N4 coating thickness of 50 μm to 150 μm and lower for 200 μm. The minority carrier lifetimes of the top, middle and bottom wafers have been analysied. The results show that the middle wafer has higher minority carrier lifetime compared to top and bottom wafers.

Investigation of orientation, surface morphology, impurity concentration and reflectivity of the multi-crystalline silicon wafers

Multi-crystalline silicon (mc-silicon) ingot was grown using the directional solidification (DS) method. The grown ingot was sliced, and the grain orientations, grain size, surface morphology, and impurities concentration in the wafers were studied. The XRD pattern of as-cut wafers exhibited the formation of a more number of (111) oriented plane in the grown ingot. The scanning electron microscopy images showed the formation of worm-like trenches after the chemical etching of the sliced wafers. FTIR spectra showed the higher carbon concentration on the top wafers and higher oxygen concentration at the bottom wafers. At the central wafer of the middle brick, the calculated carbon and interstitial oxygen concentration result exhibited 4.740 × 1016 and 1.369 × 1017 atoms/cm3, respectively. The impurity concentration of carbon and oxygen is validated with simulation results. The reflectivity spectra revealed low reflectivity for the wafers sliced from the central brick compared to the peripheral brick. The presence of very less impurity concentration and low reflectivity of the middle wafer in the central portion of the ingot enhances the light absorption, which is beneficial for photovoltaic energy generation.

Design, integration and performance analysis of a lid-integral microchannel cooling module for high-power chip

In this paper, a lid-integral silicon-based microchannel cooling module (LSMCM) for a large-sized and high-power chip was designed, fabricated, and experimentally evaluated. The silicon-based microchannel heat sink was directly attached to a thermal test vehicle by high thermal conductive thermal interface material (TIM) and assembled with the molybdenum copper alloy (Mo70Cu) manifold. Finite volume method (FVM) simulations were conducted to optimize the channels in the slit and manifold. The non-uniformity of flow velocity is 8% when the flow rate is 1 L/min. The maximum temperature difference is 4.1 °C when the heat flux is 150 W/cm2 and the flow rate is 1 L/min. Based on the simulation results, the prototype of the module was fabricated. The top slit and bottom microchannel wafers were first fabricated by deep reactive ion etching (DRIE) and then bonded by wafer-to-wafer CuSn bonding to form the microchannel heat sink. SAC305 solder paste was used to seal the manifold and the microchannel heat sink. Last, a test facility was established to test the module’s pressure drop and heat dissipation performance. The test results showed that the pressure drop is 18.3 kPa when the flow rate is 1 L/min. The thermal resistance from chip to inlet coolant is 27.1 mm2K/W and the maximum temperature difference is 6.3 °C. The average temperature rise of the thermal test chip (TTC) is 52.9 °C when the total power reaches 1200 W. Therefore, LSMCM is expected to provide high heat removal ability and be used for large-sized and high-power chip.

A Super-Resolution Model for Improving the Precision of Wafer Mark Alignment

Wafer bonding machine uses industrial camera to recognize marks on top wafer and bottom wafer, compute deviation, and move top wafer to align the bottom wafer. The alignment precision mainly depends on the camera resolution, high resolution industrial camera is expensive, while classical image up-sampling methods such as bicubic interpolation don’t have good effect. To improve the alignment precision, a super-resolution model is proposed. Main component of this model is convolutional neural network. The first two convolutional layers are to extract feature on wafer image, the next convolutional layer is used for nonlinear mapping, and the final one outputs super-resolution image. Peak Signal to Noise Ratio (PSNR) is used to evaluate the similarity of super resolution image and the target high resolution image. It’s proved by experiments that the super-resolution model has better effect than classical image interpolation methods. This research result can also be applied to other equipment using industrial cameras.

Investigation of the 6-Folded Pattern in the Facetted Region of 4° Off-Axis 4H-SiC

We demonstrate 4o off-axis 4H-SiC bulk crystal growth using physical vapor transport method (PVT). A radial 6-folded pattern is discovered in the facetted region of the growth surface by differential interference contrast microscopy. SICA88 Wafer Inspection/Review System was used to further inspect such 6-folded pattern with photoluminescence channel for wafers cut from that 4H-SiC crystal. It was found that the 6-folded pattern exists in all the wafers from the bottom to the top of that crystal. Several radial 6-folded patterns are found in the bottom wafer near the seed, but there is only one in the other two wafers. Defects distribution of these wafers after etched were also researched to find out the relationship between the radial 6-folded pattern and the defects. Based on the results, the formation and evolution mechanism of the radial 6-folded pattern on 4o off-axis 4H-SiC crystal is discussed.

Study on Forming-Free Characteristic of Amorphous Carbon Oxide Reram By Controlling Cu-Filament Shape

Resistive random access memory (ReRAM) is one of the most promising candidates for the next-generation memory due to its simple structure, high switching speed and low power consumption [1]. Recently, there has been large interests in using carbon-baed material as solid electrolyte to overcome the limit of conventional metal-oxide memory. It has remarkable advantages over past metal-oxide memory such as high memory margin (Ion/Ioff > 100) and fast switching speed (20~50ns) [2]. However, the requirement of forming process to activate resisitive switching operation is one of the critical issues. Forming process may degrade the device switching characteristic and is not desirable for circuit design. In this study, forming-free characteristic of a-COx (amorphous carbon oxide) based ReRAM was observed by controlling the Cu-filament shape. To accurately control the Cu-atom concentration profile, insertion of Cu thin film was carried out in several ways. The first device, named A, was fabricated with the common ReRAM structure of Pt / Cu-doped a-COx / W. The second device, named B, was vertically stacked with the strcutrue of Pt / a-COx / Cu-doped a-COx / W. The third device, named C, was vertically stacked with the strcutrue of Pt / Cu-doped a-COx / a-COx / Cu-doped a-COx / W. The device was fabricated on W bottom electrode wafer patterned from 34 nm to 1921 nm by photo lithography process. The a-COx and other metals were deposited using dc magnetron sputter (PVD method). After the fabrication, the Cu-atom concentration profile was carefully examined using SIMS analysis to understand the correlation between forming-free chracteristic and Cu-filament shape. Forming-free characteristic device presented identical forming and set voltage of -0.85 V. Moreover, the result indicated that the high resistance state current of 2.41-7 A at 0.1 V, low resistance state current of 5.98-5 A at 0.1 V and the memory window margin (Ion/Ioff) of 2.48×102. In our study, we present that the precise design of the Cu-atom concentration profile of a-COx based ReRAM is the significant key to achieve the forming-free and stable non-volatile memory characteristic. [1] Daniele Ielmini, Semicond. Sci. Technol. 31 (2016) 063002 [2] Claudia A. Santini et al, NAT COMMUN, 6:8600 (2015) * This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Figure 1

Investigation of air damping effect in two kinds of capacitive MEMS accelerometers

In this study, the air damping ratios of an unsealed chip of a capacitive accelerometer subjected to different pressures were measured by a special designed circuit in a static state test. There are total eight trapezoid grooves on the top and bottom electrode wafers aiming at reducing air damping effect. Finite element method based on energy balance method and transient blade row model is used to simulate in ANSYS/CFX with a new formula of effective viscosity of the air derived from simulation and validated by experimental results. The numerical results are in good agreement with the experimental results. With the same method and the new formula of effective viscosity, the air damping ratio of a new chip without trapezoid grooves is simulated as well. The comparison of the two kind of chips shows that the air damping ratio decreases 63.4% after four trapezoid grooves were engrooved on the top and bottom electrode wafers. As a result, engrooving on the top and bottom electrode wafers provides a new way to reduce air damping effect.

Controllable cracking behavior in Si/Si0.70Ge0.30/Si heterostructure by tuning the H+ implantation energy

Controllable cracking behaviors are realized in Si with a buried B doped Si0.70Ge0.30 interlayer by tuning the H+ projected ranges using the traditional H implantation technique. When the projected range is shallower (deeper) than the depth of the buried Si0.70Ge0.30 layer, cracking occurs at the interface between the top Si layer (bottom handle Si wafer) and the Si0.70Ge0.30 interlayer, thus resulting in the formation of continuous sharp crack confined at the Si0.70Ge0.30/Si interfaces. For the case that the H-ion projected range is located at the B-doped Si0.70Ge0.30 buried interlayer, continuous cracking is observed along the interlayer, which is similar to the conventional ion-cut method. We attribute these controlled cracking behaviors to the B doped Si0.70Ge0.30 interlayer, which holds a large amount of B impurities and compressive strain, and H ions can be trapped and confined at the interfaces or within the interlayer (depended on projected ranges) to facilitate the formation of cracks.

Increasing minority carrier lifetime in as-grown multicrystalline silicon by low temperature internal gettering

We report a systematic study into the effects of long low temperature (≤500 °C) annealing on the lifetime and interstitial iron distributions in as-grown multicrystalline silicon (mc-Si) from different ingot height positions. Samples are characterised in terms of dislocation density, and lifetime and interstitial iron concentration measurements are made at every stage using a temporary room temperature iodine-ethanol surface passivation scheme. Our measurement procedure allows these properties to be monitored during processing in a pseudo in situ way. Sufficient annealing at 300 °C and 400 °C increases lifetime in all cases studied, and annealing at 500 °C was only found to improve relatively poor wafers from the top and bottom of the block. We demonstrate that lifetime in poor as-grown wafers can be improved substantially by a low cost process in the absence of any bulk passivation which might result from a dielectric surface film. Substantial improvements are found in bottom wafers, for which annealing at 400 °C for 35 h increases lifetime from 5.5 μs to 38.7 μs. The lifetime of top wafers is improved from 12.1 μs to 23.8 μs under the same conditions. A correlation between interstitial iron concentration reduction and lifetime improvement is found in these cases. Surprisingly, although the interstitial iron concentration exceeds the expected solubility values, low temperature annealing seems to result in an initial increase in interstitial iron concentration, and any subsequent decay is a complex process driven not only by diffusion of interstitial iron.

Low Temperature Internal Gettering of Bulk Defects in Silicon Photovoltaic Materials

Multicrystalline silicon (mc-Si) substrates are widely used for photovoltaic cells. The minority carrier lifetime in mc-Si is affected by recombination associated with metallic impurities in many forms, such as point-like defects, precipitates and bound to or precipitated at structural defects such as dislocations. We have studied the effect of low temperature annealing on the lifetime and bulk iron concentration in as-received mc-Si wafers from different locations within a block. Lifetime measurements are made using a temporary iodine-ethanol surface passivation technique to minimize the occurrence of bulk hydrogenation which often occurs from dielectric films. In good wafers from the middle of the block the lifetime is reduced by annealing at 400 °C and 500 °C in a way which does not correlate with changes in bulk iron concentration. Lifetime improvements occur in relatively poor samples from the top and bottom of the block annealed at 300 °C, and also in samples from the bottom annealed at 400 °C. The improvement in bottom wafers correlates with iron loss from the bulk. Our work shows that under some conditions the lifetime in relatively poor as-grown wafers can be improved by low temperature internal gettering.

Pre-particle filtration and moisture control by efficient purging in various inlet and outlet of a 450 mm wafer front-opening unified pod

The trend toward narrower line width in semiconductor manufacturing has made contamination control more and more important. The presence of moisture in wafer containers, such as front opening unified pods (FOUP), can lead to the native oxide residues growth, metal corrosion, and thin film cracking on wafer surfaces. Accordingly, decreasing contamination methods and improving factory efficiency are continuously researched. Single or multi-layer particulate shields on top of wafers in FOUPs may be used to prevent pollutant accumulation. In addition, point-of-use (POU) filtration may also been used to control particle contamination in FOUPs during wafer transformation and storage. The demand for stricter filtration led to the usage of 0.10 and 0.20 µm membranes to control the contamination. However, with the introduction of finer membranes end users may have concerns about deleterious remainders on wafers from undergoing filtration. There are a total of 25 pieces of wafers in the FOUP and the arrangement is from the bottom (wafer No. 1) to the top (wafer No. 25) with arising manner. Purging FOUPs to expel moisture vapors with Clean Dry Air (CDA) is one of the most popular methods.There was no previous research for investigating the purge performance on new-generation 450mm FOUPs. This research aims to study main factors influencing the performance of the purge system on 450mm FOUPs, including moisture concentration, CDA flow rate, and filter pressure.