In this paper, a novel partial product generation (PPG) scheme has been proposed based on the shift and the add logic of multiplier bits to introduce a radix-4 and radix-16 signed binary multiplications (SBMs). The proposed PPG methodology encodes two bits for radix-4 and four bits for radix-16 at a time, whereas the traditional modified Booth encoding (MBE) for radix-4 and radix-16 encodes three bits and five bits, respectively, at a time, which offers the reduction of the encoder combinations. In the proposed design, the multiplication sign extension is pre-decided from the most significant bit (MSB) of the multiplier and the multiplicand, thereby subtraction operation for multiplication is removed from traditional MBE. The simulation results of the proposed SBMs architecture offer a significant improvement in power, delay and power-delay-product (PDP). The PDP was reduced by [Formula: see text]%, [Formula: see text]% and [Formula: see text]%, respectively, with proposed radix-4 SBM and by [Formula: see text]%, [Formula: see text]% and [Formula: see text]%, respectively, with proposed radix-16 SBM for [Formula: see text]-, and [Formula: see text]-bit multiplication, respectively, when compared with the existing state-of-the-art designs.