Boolean Circuits Research Articles

A small decrease in the degree of a polynomial with a given sign function can exponentially increase its weight and length

A Boolean function f: {−1, +1}n → {−1, +1} is called the sign function of an integer-valued polynomial p(x) if f(x) = sgn(p(x)) for all x ∈ {−1, +1}n. In this case, the polynomial p(x) is called a perceptron for the Boolean function f. The weight of a perceptron is the sum of absolute values of the coefficients of p. We prove that, for a given function, a small change in the degree of a perceptron can strongly affect the value of the required weight. More precisely, for each d = 1, 2, ..., n − 1, we explicitly construct a function f: {−1, +1}n → {−1, +1} that requires a weight of the form exp{Θ(n)} when it is represented by a degree d perceptron, and that can be represented by a degree d + 1 perceptron with weight equal to only O(n2). The lower bound exp{Θ(n)} for the degree d also holds for the size of the depth 2 Boolean circuit with a majority function at the top and arbitrary gates of input degree d at the bottom. This gap in the weight values is exponentially larger than those that have been previously found. A similar result is proved for the perceptron length, i.e., for the number of monomials contained in it.

Complexity of propositional proofs under a promise

We study—within the framework of propositional proof complexity—the problem of certifying unsatisfiability of CNF formulas under the promise that any satisfiable formula has many satisfying assignments, where many stands for an explicitly specified function Λ in the number of variables n . To this end, we develop propositional proof systems under different measures of promises (i.e., different Λ) as extensions of resolution. This is done by augmenting resolution with axioms that, roughly, can eliminate sets of truth assignments defined by Boolean circuits. We then investigate the complexity of such systems, obtaining an exponential separation in the average case between resolution under different size promises: (1) Resolution has polynomial-size refutations for all unsatisfiable 3CNF formulas when the promise is ϵ…2 n , for any constant 0<ϵ<1. (2) There are no subexponential size resolution refutations for random 3CNF formulas, when the promise is 2 Δ n , for any constant 0<δ<1 (and the number of clauses is O ( n 3/2-ϵ ), for 0<ϵ<1/2). “ Goods Satisfactory or Money Refunded ” —The Eaton Promise

An Efficient Algorithm for Constructing DNA Boolean Circuit

Computation using biological Deoxyribonucleic acid (DNA) strand is increasingly found to be a viable proposition. A unique generalized efficient algorithm for forming any Boolean circuit strand is proposed in this paper. The implementation of the Boolean circuit using the proposed algorithm is also presented. This Boolean circuit requires only one kind of bio-operation at each level. Further, this paper adopts a uniform representation for logical 0 and 1 for all Boolean circuit. Simulation to validate the efficient algorithm is also presented in this work.

A SAT Solver for Circuits Based on the Tableau Method

We present an extension of the BC tableau, a calculus for determining satisfiability of constrained Boolean circuits. We argue that a satisfiability decision procedure based on the BC tableau can be implemented as a non-clausal DPLL procedure and that therefore, advances to the DPLL framework can be integrated into such a tableau procedure. We present a prototypical implementation of these ideas and evaluate it using a set of benchmark instances. We show that the extensions increase the efficiency of the basic BC tableau considerably and compare the performance of our solver with that of the non-clausal solver NoClause and the CNF-based SAT solver MiniSat.

New upper bounds on the Boolean circuit complexity of symmetric functions

In this note, we present improved upper bounds on the circuit complexity of symmetric Boolean functions. In particular, we describe circuits of size 4.5 n + o ( n ) for any symmetric function of n variables, as well as circuits of size 3 n for MOD 3 n function.

Translating propositional extended conjunctions of Horn clauses into Boolean circuits

H o r n ⊃ is a logic programming language which extends usual H o r n clauses by adding intuitionistic implication in goals and clause bodies. This extension can be seen as a way of structuring programs in logic programming. We are interested in finding correct and efficient translations from H o r n ⊃ programs into some representation type that, preserving the signature, allows us suitable implementations of these kinds of programs. In this paper we restrict to the propositional setting of H o r n ⊃ and we study correct translations into Boolean circuits, i.e. graphs; into Boolean formulas, i.e. trees; and into conjunctions of propositional H o r n clauses. Different results for the efficiencies of the transformations are obtained in the three cases.

Block-sequential update schedules and Boolean automata circuits

Our work is set in the framework of complex dynamical systems and, more precisely, that of Boolean automata networks modeling regulation networks. We study how the choice of an update schedule impacts on the dynamics of such a network. To do this, we explain how studying the dynamics of any network updated with an arbitrary block-sequential update schedule can be reduced to the study of the dynamics of a different network updated in parallel. We give special attention to networks whose underlying structure is a circuit, that is, Boolean automata circuits. These particular and simple networks are known to serve as the "engines'' of the dynamics of arbitrary regulation networks containing them as sub-networks in that they are responsible for their variety of dynamical behaviours. We give both the number of attractors of period $p$, $\forall p\in \mathbb{N}$ and the total number of attractors in the dynamics of Boolean automata circuits updated with any block-sequential update schedule. We also detail the variety of dynamical behaviours that such networks may exhibit according to the update schedule.

Equivalent forms of single-operational transconductance amplifier RC oscillators with application to grounded-capacitor oscillators

It is shown that, given a single-operational transconductance amplifier (OTA) resistor-capacitor (RC) sinusoidal oscillator circuit, it can be put in three other, structurally distinct forms without altering its characteristic equation. This result may facilitate the transformation of some of the available single-OTA RC oscillators employing floating capacitors into the desirable form of employing grounded capacitors. The result turns out to be an aid to a Boolean circuit synthesis method previously given by Tao and Fidler for the generation of single-OTA RC oscillators.

Probabilistic Verification over GF(2m) Using Mod2-OBDDs

Formal verification is fundamental in many phases of digital systems design. The most successful verification procedures employ Ordered Binary Decision Diagrams (OBDDs) as canonical representation for both Boolean circuit specifications and logic designs, but these methods require a large amount of memory and time. Due to these limitations, several models of Decision Diagrams have been studied and other verification techniques have been proposed. In this paper, we have used probabilistic verification with Galois (or finite) field GF(2m) modifying the CUDD package for the computation of signatures in classical OBDDs, and for the construction of Mod2-OBDDs (also known as ?-OBDDs). Mod2-OBDDs have been constructed with a two-level layer of ?-nodes using a positive Davio expansion (pDE) for a given variable. The sizes of the Mod2-OBDDs obtained with our method are lower than the Mod2-OBDDs sizes obtained with other similar methods.

Simulation of one-way cellular automata by boolean circuits

We present a relationship between two major models of parallel computation: the one-way cellular automata and the boolean circuits. The starting point is the boolean circuit of small depth designed by Ladner and Fischer to simulate any rational transducer. We extend this construction to simulate one-way cellular automata by boolean circuits.

Parallelizing Time with Polynomial Circuits

We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing time t random access Turing machines, a model at least as powerful as logarithmic cost RAMs. Our parallel simulation yields logspace-uniform t O(1) size, O(t/log t)-depth Boolean circuits having semi-unbounded fan-in gates. In fact, for appropriate d, uniform t O(1)2O(t/d) size circuits of depth O(d) can simulate time t. One corollary is that every log-cost time t RAM can be simulated by a log-cost CRCW PRAM using t O(1) processors and O(t/log t) time. This improves over previous parallel speedups, which only guaranteed an Ω(log t)-speedup with an exponential number of processors for weaker models of computation. These results are obtained by generalizing the well-known result that $\textsf{DTIME}[t]\subseteq \textsf{ASPACE}[\log t]$.

The complexity and depth of Boolean circuits for multiplication and inversion in some fields GF(2 n )

Let n = (p − 1) · pk, where p is a prime number such that 2 is a primitive root modulo p, and 2p−1 − 1 is not a multiple of p2. For a standard basis of the field GF(2n), a multiplier of complexity O(log log p)n log n log logpn and an inverter of complexity O(log p log log p)n log n log logpn are constructed. In particular, in the case p = 3 the upper bound $$ 5\frac{5} {8}n\log _3 n\log _2 \log _3 n + O(n\log n) $$ for the multiplication complexity and an upper bound for the inversion complexity which is asymptotically 2.5-times greater are obtained (hereafter, if not indicated explicitly, all logarithms are base two).

Representing (0, 1)-matrices by boolean circuits

A boolean circuit represents an n by n ( 0 , 1 ) -matrix A if it correctly computes the linear transformation y → = A x → over GF(2) on all n unit vectors. If we only allow linear boolean functions as gates, then some matrices cannot be represented using fewer than Ω ( n 2 / ln n ) wires. We first show that using non-linear gates one can save a lot of wires: any matrix can be represented by a depth- 2 circuit with O ( n ln n ) wires using multilinear polynomials over GF(2) of relatively small degree as gates. We then show that this cannot be substantially improved: If any two columns of an n by n ( 0 , 1 ) -matrix differ in at least d rows, then the matrix requires Ω ( d ln n / ln ln n ) wires in any depth- 2 circuit, even if arbitrary boolean functions are allowed as gates.

The inverse Banzhaf problem

Let \({\mathcal{F}}\) be a family of subsets of the ground set [n] = {1, 2, . . . , n}. For each \({i \in [n]}\) we let \({p(\mathcal{F},i)}\) be the number of pairs of subsets that differ in the element i and exactly one of them is in \({\mathcal{F}}\). We interpret \({p(\mathcal{F},i)}\) as the influence of that element. The normalized Banzhaf vector of \({\mathcal{F}}\), denoted \({B(\mathcal{F})}\), is the vector \({(B(\mathcal{F},1),\dots,B(\mathcal{F},n))}\), where \({B(\mathcal{F},i)=\frac{p(\mathcal{F},i)}{p(\mathcal{F})}}\) and \({p(\mathcal{F})}\) is the sum of all \({p(\mathcal{F},i)}\). The Banzhaf vector has been studied in the context of measuring voting power in voting games as well as in Boolean circuit theory. In this paper we investigate which non-negative vectors of sum 1 can be closely approximated by Banzhaf vectors of simple voting games. In particular, we show that if a vector has most of its weight concentrated in k < n coordinates, then it must be essentially the Banzhaf vector of some simple voting game with n − k dummy voters.

Limiting negations in non-deterministic circuits

The minimum number of NOT gates in a Boolean circuit computing a Boolean function f is called the inversion complexity of f . In 1958, Markov determined the inversion complexity of every Boolean function and, in particular, proved that ⌈ log 2 ( n + 1 ) ⌉ NOT gates are sufficient to compute any Boolean function on n variables. In this paper, we consider circuits computing non-deterministically and determine the inversion complexity of every Boolean function. In particular, we prove that one NOT gate is sufficient to compute any Boolean function in non-deterministic circuits if we can use an arbitrary number of guess inputs.

Perceptrons of large weight

A threshold gate is a linear combination of input variables with integer coefficients (weights). It outputs 1 if the sum is positive. The maximum absolute value of the coefficients of a threshold gate is called its weight. A degree-d perceptron is a Boolean circuit of depth 2 with a threshold gate at the top and any Boolean elements of fan-in at most d at the bottom level. The weight of a perceptron is the weight of its threshold gate. For any constant d ≥ 2 independent of the number of input variables n, we construct a degree-d perceptron that requires weights of at least $$ n^{\Omega (n^d )} $$; i.e., the weight of any degree-d perceptron that computes the same Boolean function must be at least $$ n^{\Omega (n^d )} $$. This bound is tight: any degree-d perceptron is equivalent to a degree-d perceptron of weight $$ n^{O(n^d )} $$. For the case of threshold gates (i.e., d = 1), the result was proved by Hastad in [2]; we use Hastad’s technique.

Prediction of Pairwise Gene Interaction Using Threshold Logic

The two important problems of computational biology are the modeling of gene regulatory networks and the study of the network structure of complex biological systems. There is an increased use of mathematical and computational theory techniques to solve both these problems. The Boolean circuit model is one of the most popular modeling paradigms used to model gene regulatory networks. In this paper we try to make use of the properties of threshold logic (an alternative to Boolean logic to design digital circuits) to determine the network structure of gene systems. This approach uses the gene-expression data from microarray experiments as input. The proposed method was first used to build the gene network for a set of genes, proteins, and other molecular components based on in silico data. Then, the method was applied to a biological dataset to build the gene regulatory network for a core set of genes associated with melanoma. Some of the interactions found could be verified by earlier biological experiments reported in published literature. Other interactions that could not be validated by existing biological knowledge can provide insights into the investigation of bio-chemical pathways associated with melanoma development.

The complexity of depth-two information networks

The lower bound Ω(n log2n) for the complexity of an arbitrary depth-two information network with n inputs and n outputs is proved providing the inputs are independent, the outputs are independent, and the total information of any input and any output is n times less than the entropy of any input or output. A similar estimate for Boolean depth-two circuits of functional elements is obtained as a corollary.

Boolean circuit programming: A new paradigm to design parallel algorithms

The Boolean circuit has been an important model of parallel computation, but not many parallel algorithms have been designed on this model because it is ‘awkward to program.’ To overcome this drawback, we propose a description language for designing parallel algorithms on the Boolean circuit. This description language is to parallel algorithms what the pseudo-code is to sequential algorithms. Through example codes, we show that the description language is a convenient tool to design parallel algorithms due to its general iterative and recursive structures and the ease of modular design.

Faster Integer Multiplication

For more than 35 years, the fastest known method for integer multiplication has been the Schonhage-Strassen algorithm running in time $O(n\log n\log\log n)$. Under certain restrictive conditions, there is a corresponding $\Omega(n\log n)$ lower bound. All this time, the prevailing conjecture has been that the complexity of an optimal integer multiplication algorithm is $\Theta(n\log n)$. We take a major step towards closing the gap between the upper bound and the conjectured lower bound by presenting an algorithm running in time $n\log n\,2^{O(\log^*n)}$. The running time bound holds for multitape Turing machines. The same bound is valid for the size of Boolean circuits.