Bonded And Etched-back Silicon-on-insulator Research Articles

Silicon-On-Diamond layer integration by wafer bonding technology

In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management. We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200 nm to 7000 nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50 mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5 µm thick diamond layer could be reduced from 50 to 3 nm RMS and down to 1.5 nm RMS for a thin 200 nm layer. In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC. Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70 nm) of 50 mm diameter onto a 140 nm thick diamond BOX layer has been transferred on 200 mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.

Electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

Electrical test structures known as cross-bridge resistors have been patterned in [100] epitaxial silicon material that was grown on Bonded and Etched-back Silicon-On-Insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically, by scanning-electron microscopy (SEM), and by lattice-plane counting. The lattice-plane counting is performed on phase-contrast images of the cross sections of the reference segments that are produced by high-resolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with [110] directions in the BESOI surface material. They were defined by a silicon micromachining process that resulted in their sidewalls being nearly atomically planar and smooth and inclined at 54.737/spl deg/ to the surface [100] plane of the substrate. SEM, HRTEM, and electrical CD (ECD) linewidth measurements have been made on features of various drawn dimensions on the same substrate to investigate the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of ECD metrology and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the [100] silicon-on-insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of lattice-plane counts from cross-sectional HRTEM imaging of the reference features. This paper describes the design details and the fabrication of the cross-bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross-bridge resistors' reference segments, as a prelude to making them available for dimensional reference applications.

Silicon-based microelectrodes for neurophysiology, micromachined from silicon-on-insulator wafers.

A process is described for the fabrication of silicon-based microelectrodes for neurophysiology using bonded and etched-back silicon-on-insulator (BESOI) wafers. The probe shapes are defined without high levels of boron doping in the silicon; this is considered as a step towards producing probes with active electronics integrated directly beneath the electrodes. Gold electrodes, of 4 microns by 4 microns to 50 microns by 50 microns are fabricated on shanks (cantilever beams) 6 microns thick and which taper to an area approximately 100 microns wide and 200 microns long, which are inserted into the tissue under investigation. The passive probes fabricated have been successfully employed to make acute recordings from locust peripheral nerve.

Measurement of carrier generation lifetime in SOI devices

This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and the three types of the SOI wafers are shown to have a lifetime variation of ±20% across four inch wafers. The generation lifetime was also found to depend on the device fabrication process.

MOS-compatible fabrication and characterization of tunnel junctions in BESOI-material

We present a fabrication technique for single electron tunnel junctions in silicon. Based on Bonded and Etched back Silicon On Insulator (BESOI) material with a very thin silicon top layer tunnel junctions are realized by electron beam lithography (EBL) in combination with a two-layer resist system. The pattern is transferred by anisotropic reactive ion etching (RIE). The lateral dimensions are reduced further by thermal oxidation in a subsequent step. The process technology is, apart from the e-beam lithography, fully MOS compatible. Different samples with four tunnel junctions in series were characterized at 6 K. The I/U-characteristics reveals a Coulomb blockade as well as a Coulomb staircase, which can be attributed to the asymmetrical structure. By realizing a backgate configuration periodic modulations in the source drain current versus the gate voltage have been measured.

A simple technique to measure generation lifetime in partially depleted SOI MOSFETs

This work presents a new, simple method of measuring the generation lifetime in silicon-on-insulator (SOI) MOSFETs. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (Separation by IMplantation of OXygen) wafers and BESOI (Bonded and Etchedback SOI) wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and both the SIMOX and the BESOI are shown to have a lifetime variation of /spl plusmn/10% across four inch wafers.

A triangle-shaped nanoscale metal–oxide–semiconductor device

A new fabrication process for ultrasmall high-current-density metal–oxide–semiconductor transistors is proposed. The device fabrication is based on anisotropic wet etching of silicon using bonded and etched back silicon-on-insulator (BESOI) material and a self-adjusting polysilicon gate technology. The special feature in the design of the transistor is a small silicon wire with a triangular instead of a planar cross section connecting the source and drain areas. Applying a moderate voltage to the poly-gate, a high electric field is built up in the top of the triangle which increases the volume of the conducting channel below the gate. For normal operating conditions, the three-dimensional current flow allows smaller lateral dimensions of the device that offers higher integration. Because of the BESOI material, faster device performance is expected. The physical principle is discussed and the basic fabrication techniques are described. First electrical investigations of the transistors operating at room temperature are presented providing evidence that the current density is considerably higher than in planar transistors.

Bulk silicon microelectromechanical devices fabricated from commercial bonded and etched-back silicon-on-insulator substrates

Abstract In this work a new and simple technology for the fabrication of bulk silicon microelectromechanical devices is presented. The microstructures are defined in the silicon active layer of commercially available bonded and etched-back silicon-on-insulator (BESOI) substrates by a single photolithographic step and anisotropic dry etching. The thickness of the structures is only limited by the performance of the dry-etching process. In this work a thickness of 20 μm is used. Various devices have been fabricated, including electrostatic micromotors, microturbines and electrostatically actuated microrelays. An interesting feature of this technology is that the use of BESOI substrates allows the integration of electronic circuits on the substrate used to fabricate the microelectromechanical devices.

Charge Instability of Bonded Silicon Dioxide Layer Induced by Wet Processing

The charging of buried oxide (BOX) of bonded and etched‐back silicon‐on‐insulator (BESOI) structures caused by electrical stress was studied. The top Si layer was removed and the structures with bare oxide were immersed in before evaporation of aluminum. This treatment results in an ion‐type charge instability effect observed at room temperature. If the top Si layer was removed by dry etching or not removed at all, then the structures do not exhibit a comparable effect even at 250°C; neither do wet‐treated nonbonded thermal layers. Replacement of by delays the ionic charge buildup, suggesting an isotopic effect. It is suggested that the high‐temperature postbonding anneal results in structural change in the BOX layer which promotes the transport of hydrogen‐related charged species.

Effect of buried Si-SiO2 interfaces on oxidation and implant-enhanced dopant diffusion in thin silicon-on-insulator films

The diffusion behavior of phosphorus and boron was used to study point defect kinetics in silicon-on-insulator (SOI) material. Phosphorus marker layers were used to study oxidation enhanced diffusion in bulk and bonded and etched-back silicon-on-insulator (BESOI) material under oxidizing conditions at 750, 800, and 850 °C. An effective interstitial recombination velocity Kox for the buried Si-SiO2 interface in the BESOI material was extracted by fitting the experimentally obtained phosphorus profiles with suprem−iv simulation results. The data can be modeled with a time-independent interface recombination velocity. The same parameter set incorporating this extracted recombination velocity was used to accurately model the implant enhanced diffusion of boron marker layers at 750 and 800 °C in thin SOI films, implying the recombination velocity is independent of the interstitial supersaturation. The expression Kox/DI=4.7×10−3 exp(+1.34/kT) fits this work and also a wide range of literature results at higher temperatures.