Bond Pad Thickness Research Articles

A computational study of the effect of bond pad thickness on the polysilicon piezoresistivity due to wafer level probing

Polysilicon is an integral part of many devices in all CMOS processes. Circuit Under Pad (CUP) devices are required to have consistent and accurate electrical performance just like any other device. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options (METMID and METTHK) on a polysilicon resistor placed under the bond pad. Wafer level probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance (piezoresistivity) of a polysilicon resistor which was placed underneath the bond pads. A commercial finite element analysis software (Comsol Multiphysics) was used to predict the stress distribution in the polysilicon device, followed by experimental validation of the electrical resistance. It was observed that the bond pad thickness can influence the residual stress which in turn causes a change in resistance after wafer level probing. However, for each bond pad thickness, multiple probe insertions did not significantly change the resistance of the device placed under the bond pad.

Effects of Bond Pad Thickness on Shear Strength of Copper Wire Bonds

Abstract Copper (Cu) wire bonding is now widely accepted as a replacement for gold (Au), however, its use in high reliability applications is limited due to early failures in high temperature and humid conditions. The Au to Cu wire transition is mainly driven by cost savings though there are other advantages to Cu such as better electrical and thermal conductivity, slower intermetallic compound (IMC) formation and reduced wire sweep during transfer molding. Some automotive, industrial and aerospace industries are still reluctant to adopt Cu wire bonded products due to perceived risks of wire and bond pad cracks, the potential for corrosion, and some lack of understanding about its reliability in harsh conditions. A wire bond is considered good if destructive sampling qualification tests and periodic monitors pass for the batch. Tests include wire pull strength, wire bond shear, IMC coverage, and thickness of bond pad aluminum (Al) remaining beneath the bond. Nondestructive inspections also verify acceptable ball diameter and Al “splash”. This paper focuses on the bond shear test and its contribution to Cu ball bond reliability assessment, especially when changing Al bond pad thickness. A new revision of the JEDEC Wire Bond Shear Test Method, JESD22-B116B, has just been released, to include Cu wirebonds for the first time. It helps to clarify shear test failure modes for Cu ball bonds. However, there are still questions to be answered through research and experimentation, especially to learn the extent to which one may predict Cu ball bond reliability based on shear test results. Pad Al thickness is not considered in the current industry standards for shear test. Yet bond pad Al thickness varies widely among semiconductor products. This research is intended to contribute toward improved industry standards. In this study, power and time bonding parameters along with bond pad thickness are studied for bond strength. Several wire bonds are created at different conditions, evaluated by optical microscope and SEM, IMC% coverage and bond shear strength. Similar bonding conditions are repeated for bond pads of 4um, 1um and 0.5um thickness.

Effect of Cu and PdCu wire bonding on bond pad splash

Cu wire bonding research has exploded exponentially in the past few years. Many studies have been carried out to understand the different behaviours of Cu wire and Au wire. One of the observations on Cu wire bonding is the excessive formation of aluminium (Al) splash on the bond pad due to a higher bond force. This leads to pad peeling and bond failure resulting in poor reliability performance of Cu and PdCu wire semiconductor devices. It is known that the Al splash is influenced by the front-end pad metal process and back-end wire bond process. Reported is the design of an experiment carried out to study a few factors that could influence the Al splash. The characterisation work is implemented to understand the bond pad structure using the focused ion beam (FIB) followed by a hardness test of bond pad metallisation. Then the mechanical cross-section is taken to measure the Al splash in three different directions. The results show that Al splash can be controlled by optimising the bond pad thickness, hardness and additive for reliable Cu and PdCu wire bonding.

Finite Element Analysis of Copper Wire Bonding in Integrated Circuit Devices

Axisymmetric finite element models of copper wire-bond-pad structure for an integrated circuit devicewere developed to investigate theeffects of bonding force, initial bonding temperature, Aluminum metallization thickness, bond pad thickness and free air ball (FAB) diameter on induced stresses in the wire-bond structure. The results show that an increase in bonding force greatly increased the induced stresses in the copper FAB and bond pad (aluminum and silicon). However, a change in bonding temperature while keeping the bonding force constant does not result in an appreciable change in the stress. Similarly an increase in aluminium metallization thickness does not yield appreciable variation in the stress and strain in the bond pad. Over the range of FAB diameters studied it is found that bigger FAB yields smaller stress in the overall structure

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis

In this paper, a transient nonlinear dynamic finite element framework is developed, which integrates the wire bonding process and the silicon devices under bond pad. Two major areas are addressed: one is the impact of assembly 1st wire bonding process and another one is the impact of device layout below the bond pad. Simulation includes the ultrasonic transient dynamic bonding process and the stress wave transferred to bond pad device and silicon in the 1st bond. The Pierce strain rate dependent model is introduced to model the impact stain hardening effect. Ultrasonic amplitude and frequency are studied and discussed for the bonding process. In addition, different layouts of device metallization under bond pad are analyzed and discussed for the efforts to reduce the dynamic impact response of the bond pad over active design. Modeling discloses the stress and deformation impacts to both wire bonding and pad below device with strain rate, different ultrasonic amplitudes and frequencies, different friction coefficients, as well as different bond pad thickness and device layout under pad. The residual stress, after cooling down to a lower temperature, is discussed for the impact of substrate temperature.

Numerical Study of Gold Wire Bonding Process on Cu/Low-k Structures

A 2D transient nonlinear finite-element (FE) analysis of thermo sonic wire bonding process on Al-capped Cu/low-k structure is carried out to understand the deformations of bond pad and the responses of structure under bond pad. An FE methodology is established that includes the ultrasonic vibration of the capillary and the analysis is studied at the impacting stage of the wire bonding process. The FE framework allowed for the detailed study of stress evolution in the Cu/low-k structure during the process in order to elucidate the evolved stresses due to the deformation behavior of the bond pad. A comparative study between bonding process on Al-capped and Au-capped low-k structures is also conducted. Effect of variation of frictional coefficients, low-k and undoped silicon glass (USG) modulus and bond pad thickness, on low-k layers and bond pad are investigated to observe their mechanical responses. The effect of implementation of porous low-k material is also highlighted and its presence is shown to increase the sinking of bond pad by a considerable amount. Analysis of the FE calculations together with experimental results suggested some optimal parameters for the bonding process.