Board Level Solder Joint Reliability Research Articles

Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in- Package (SiP) Modules

System-in-package (SiP) modules are widely used in portable electronics such as Internet of Things (IoT) devices and mobile consumer equipment since they integrate multiple components in a single package and thus facilitate device miniaturization. An advanced packaging technology referred to as dual-side molding (DSM) has recently been proposed as a means of achieving even smaller form factors and lower cost solutions. However, shrinking the package size reduces the solder joint connection area between the SiP module and the printed circuit board (PCB). Consequently, the board-level drop reliability may be severely impaired. Accordingly, the present study utilizes a numerical model to investigate the board-level solder joint reliability of a DSM SiP package in drop impact tests performed in accordance with the Joint Electron Device Engineering Council (JEDEC) standard. The validity of the numerical model combined with a full-factorial design method is then employed to examine the effects of the main design parameters of the DSM SiP package on the reliability of the solder joints in the drop impact test. Overall, the present results show that a higher EMC coverage of the solder ball joints yields a significant improvement in the solder joint reliability. In addition, a larger solder joint volume is beneficial in reducing the solder joint stress by absorbing a greater proportion of the impact load and energy produced in the drop impact event.

Thermal and Mechanical Characterization of 2.5-D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages

Heterogeneous integration technology makes possible the integration of multiple separately manufactured components into a single higher level assembly with enhanced functionality and improved operating characteristics. Various types of advanced heterogeneous packages are available, including 2.5-D integrated circuit (IC), fan-out chip on substrate (FOCoS) chip-first, and FOCoS chip-last. This study constructs a nonlinear simulation technique (3-D simulation model) to explore the warpage, extreme low-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> (ELK) interconnect stress, redistribution layer (RDL) trace stress, and board-level solder joint reliability of all three packages. The validity of the simulation model is confirmed by comparing the numerical results for the in-plane dimensional change of an FOCoS chip-last package with the experimental observations over the temperature range of 30 &#x00B0;C&#x2013;260 &#x00B0;C. The thermal performance (i.e., junction-to-ambient thermal resistance) of the three packages is then examined and compared. Finally, <inline-formula> <tex-math notation="LaTeX">$2^{5}$ </tex-math></inline-formula> factorial designs with the analysis of variance (ANOVA) are conducted to examine the effects of the main structural design parameters of the FOCoS chip-last package on its thermomechanical reliability under typical thermal loading conditions. It is shown that a thinner polyimide (PI) layer is beneficial in improving the package reliability by minimizing the coefficient of temperature expansion (CTE) mismatch between the PI layer and the RDL trace, respectively.

MAXQFP: NXP's new package solution for automotive application

Abstract 172-lead (16x16 mm body size) and 100-lead (10x10 mm body size) MAXQFP's and 172 MAXQFP_EP (exposed pad) for automotive industry are introduced. The advantage of MAXQFP as compare to standard LQFP/QFP packages will be outlined. Thermal &amp; mechanical simulation results were performed to prove its advantage over conventional LQFP and LQFP_EP. The challenges in manufacturing, designs and concerns of tighter lead pitches for MAXQFP are briefly addressed. Methods and data to resolve these challenges will be shown. For example, Sn whisker and Sn migration both are concerns to MAXQFP because of smaller distance between adjacent leads. The board-level solder joint reliability (SJR) has been collected to prove it is AEC G1 compliant. Visual inspection methods and requirements on AOI (automatic object inspection) systems on solider joints of J-leads of MAXQFP for are proposed. Standard AEC G1 component level reliability stresses defined at AEC Q100 which are TC (temperature cycling), HTSL (high temperature storage life), THB (Temperature Humidity Biased) and uHAST (un-biased HAST) tests are summarized Since Cu wires were used, AEC Q006 data are also collected. Assembly challenges are described. Future works will be summarized.

Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package

Fan-out (FO) packages are widely used in handheld, mobile consumer, and Internet of Things (IoT) devices due to the facility they provide for a greater I/O density and the integration of multiple components in a single package. Various types of FO package are available, including embedded wafer-level BGA (eWLB), fully molded (FM), and a flip-chip-based structure referred to as a fan-out chip-last package (FOCLP). In this paper, ANSYS simulations are performed to examine the warpage, extreme low- $k$ (ELK) interconnect stress and board-level solder joint reliability of the various package types. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the eWLB and FM packages with the experimental observations. Further simulations are then performed to investigate the heat dissipation performance and electrical crosstalk properties of the three packages. Taguchi experiments are conducted to examine the effects of eight control factors [namely, the inclusion (or otherwise) of a backside laminate film, the board thickness, the joint standoff distance, the ball joint diameter, the under bump metallurgy (UBM) diameter, the joint pitch, the die thickness, and the Cu pillar height] on the thermomechanical reliability of the FM package under accelerated thermal cycling testing. Finally, the Taguchi analysis results are used to determine the optimal geometry design of the FM package.

Study on Warpage and Reliability of Fan-Out Interposer Technology

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.

Four-point bending cycling: The alternative for thermal cycling solder fatigue testing of electronic components

This paper deals with an alternative testing approach for quantifying the life time of board level solder joint reliability of components. This approach consists of applying a relative shear displacement between component and Printed Circuit Board (PCB) through cyclic board bending. During the cycling, the temperature is kept constant, preferably at elevated temperature in order to accelerate the creep deformation of the solder joint. This is done in a four-point bending setup which allows to apply an equal loading on all components lying between the inner bars. The scope of the paper is, firstly, to evaluate if the four point bending testing generates the same fatigue fracture as in thermal cycling; secondly, that the measured life times can be also predicted through finite element simulations; and thirdly if the technique can finally accelerate the cycling frequency to reduce the testing time.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

PBGA Cost Reduction by Reducing Plated Au Thickness of Substrate Pads

In the past decade, we have witnessed the significant increase of gold price. Coupled with continuous price decrease of electronic products, the reduction of gold consumption has been explored in every possible area. This paper is related to reducing gold consumption on wire bonding pads of low density interconnect substrates. A layer of gold is plated on the substrate pads with typical minimum thickness of 0.5um to facilitate wire bonding process using gold wire. The objective of this study was to reduce gold thickness on the substrate pad to 0.3um minimum without compromising wire bond integrity. DOE considering different substrate sources wire bonded by different assembly suppliers were conducted. Wire bonding process optimization was followed by package level reliability stress testing, heat aging, and board level solder joint reliability testing was carried out for validation. The results showed plated gold thickness on the wire bond substrate pads can be reduced to a minimum of 0.3um without compromising package reliability performance. With the success of thinner gold on the substrate pads, we can use the same natural resources - gold to build more units, 'better for environment, if we consume less'

Board-Level Solder Joint Reliability Study of Land Grid Array Packages for RF Application Using a Laser Ultrasound Inspection System

Microelectronics packaging technology has evolved from through-hole, and bulk configuration to surface-mount, and small-profile ones. Today’s electronics industry is also transiting from SnPb to Pb-free to meet environmental requirements. Land grid array (LGA) package has been becoming popular in portable electronics in terms of low profile on the printed wiring boards and direct Pb-free assembly process compatibility. With the package profile shrinking and operating power increasing, solder joint quality and reliability has become a major concern in microelectronics manufacturing. The solder joint failure at the package level or board level will cause electronic devices not to function during service. In this paper, board-level solder joint reliability of the LGA packages under thermal loading is studied through thermal cycling tests. A novel laser ultrasound-interferometric system developed by the authors is applied to inspect solder joint quality during the thermal cycling tests. While the laser ultrasound inspection technique has been successfully applied to flip chips and chip scale packages, this study is the first application of this technique to overmolded packages. In this study, it is found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints. The laser ultrasound inspection results match the visual observation and X-ray inspection results. This study demonstrates the feasibility of this system to solder joint quality inspection of overmolded packages. In particular, the devices constituting the objective of this study are radio frequency modules, which are encapsulated through overmolding and are mounted on a typical four-layer FR4 board through LGA terminations.

Design of Experiments for Board-Level Solder Joint Reliability of PBGA Package Under Various Manufacturing and Multiple Environmental Loading Conditions

A design of experiments was conducted to determine the reliability of plastic ball grid array packages under various manufacturing and multiple environmental loading conditions. Parameters included conformal coating methods, underfill, solder mask defined, and non-solder mask defined pads. Board-level temperature cycling, vibration, and combined temperature cycling and vibration testing were performed to quantify the reliability and identify preferred design parameters. Through the main effects and interaction analysis, test results show underfill is the key parameter related to the solder joint reliability improvement. Conformal coat method and printed circuit board pad design are not main effects on solder joint reliability. No interactive relationship exists among these three factors under temperature cycling loading, but some interactive relationship between printed circuit board pad type and the conformal coating method exists under vibration and combined loading conditions.

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.

Modeling and Simulation of Electronic Packages Subjected to Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers, especially for handheld electronic products. These handheld electronic products are more prone to being dropped during their useful service life because of their small size and light weight. The electronic packages used in portable devices are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The dropping events not only induce mechanical failures in the housing of the device, but also lead to failure of PCB and components mounted on it. This work deals with: (a) Development of a simulation model of complete drop block with printed circuit board and plastic ball grid array (PBGA) assembly, which resembles actual drop test (free fall); (b) Development of an Input-G method for simulating the PCB dynamic responses; and (c) Comparison of results of free fall and Input-G methods. From the simulation results it was found that the mechanical shock causes multiple PCB bending and induce stresses in the solder balls of PBGA package. The solder balls at the outer rows of the PBGA package were subjected to maximum stress. Comparison of free fall drop and Input-G method results revealed that, the Input-G method uses less computer memory, takes less time to solve and it is simple to simulate the drop process.

Global-to-Local Modeling and Experiment Investigation of HFCBGA Package Board-Level Solder Joint Reliability

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.

Evaluation of solder joint strengths under ball impact test

The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, the BIT apparatus, characteristics of measured impact force profiles, and induced failure modes are introduced. We also present BIT results conducted on 63Sn–37Pb, 95.5Sn–4Ag–0.5Cu, and 98.5Sn–1Ag–0.5Cu package-level solder joints, bonded on substrate pads of different surface finishes, under an impact velocity of 1 m/s or 1.25 m/s.

Insights Into Correlation Between Board-Level Drop Reliability and Package-Level Ball Impact Test Characteristics

The ball impact test (BIT) is developed based on the demand of a package-level measure for the board-level drop reliability of solder joints in the sense that it leads to fracturing of solder joints around the intermetallics, similar to that from a board-level drop test. In this paper, both board-level drop test and package-level ball impact test are examined numerically for solder joints of different Sn-Ag-Cu compositions. We propose a stress-based drop reliability index that involves the strength of intermetallics and the maximum interfacial normal stress the solder joints have experienced during the drop impact process. Correlations between the drop reliability index and BIT characteristics are found to be dependent on solder compositions. However, the correlations appear to be universal, i.e., independent of solder compositions, when certain constant multipliers are introduced

Effects of solder alloy constitutive relationships on impact force responses of package-level solder joints under ball impact test

The ball impact test was developed as a package-level measure for the board-level drop reliability of solder joints in the sense that it leads to fracturing of solder joints around intermetallics, similar to that from a board-level drop test. We investigated numerically the effects of constitutive relationships of solder alloy on transient structural responses of a single package-level solder joint subjected to ball impact testing. This study focused on the characteristics of the ascending part of the impact force profile. According to the piecewise linear stress-strain curve obtained for the Sn-4Ag-0.5Cu solder alloy, parametric studies were performed by varying either segmental moduli or characteristic stresses of the curve at fixed ratios, with regard to the lack of available rate-dependent material properties of solder alloys.

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests