The transition from planar Metal-Oxide-Semiconductor (MOS) transistor architecture to 3 Dimension (3D) Field Electron Transistor (FET) architecture has been necessary to pursue transistor scaling and overcome high power consumption of logic chip. Today, the Fin Field Electron Transistor (FinFET) structure is used in the most advanced (16-/14-nm generation) CMOS technologies.[1] To continue device scaling at least to the 5nm technology node, new 3D designs, such as GAA FEt are anticipated to be adopted in the future CMOS technology generations in order to provide for superior electrostatic integrity.[2] 3D MOS architectures bring their own set of challenges for etch applications. While planar devices relied more on anisotropic etching, 3D devices require more isotropic etch capabilities with high selectivity between different materials and a nanometric precision of the etching. This work proposes a new route to achieve selective etching using a prototype of reactor combining in the same chamber a remote plasma source (RPS) and a capacitively coupled plasma (CCP) source. The proposed approach relies on cycling a two-step process comprising a functionalization step and a selective removal step of the functionalized surface over the non-functionalized one. If isotropic selective etching is needed, the chemical and isotropic action of the radicals produced in the remote plasma is used to selectively functionalize the material surfaces. On the other side, if topographically-selective etching is needed, the horizontal surfaces are selectively functionalized over vertical surfaces by using implantation of ions produced by the CCP source. The subsequent removal step uses the high selective capability of remote plasma processes (cf. Figure 1). The cycling of those two steps allows the nanometric control of the etching. The concept is inspired by what is already done in the field of atomic layer deposition (ALD) to make selective deposition. [3] [4] The current trend in ALD is to chemically and locally bond a molecule directly to the surface in order to inhibit reactive sites and then prevent further reactions between the ALD precursor molecules. By selectively functionalizing the surface of the materials in presence, selective deposition can be obtained. In our case, it happens that remote plasma processes whose etching mechanisms rely on the action of chemical plasma neutrals are very sensitive to the chemistry of the substrate. By modifying the material surface state with a treatment, the etching can be delayed or even suppressed, converting a non-selective surface into one for which the etching process is area selective. The concept is validated in two case studies. First, it is developed to achieve the isotropic and selective removal of SiGe relative to Si layers in order to fabricate horizontal stacked-Si nanowires for Gate All Around devices. For this particular application, the two-step process is composed of an oxidation step using remote He/O2 remote plasma and an etching step using remote NH3/NF3/O2 remote plasma. It is shown that the Si oxidation during the first step delay or even suppress the Si etching in NH3/NF3/O2 plasma during the second step, allowing very high SiGe over Si selectivity (>60). Secondly, it is applied to the topographically-selective Nitride spacer etching. In this case, the horizontal nitride surfaces were functionalized by H2 ion implantation and the removal step used NH3/NF3/He remote plasma process. Indeed, while pristine SiN is not etched in NH3/NF3/He remote plasma, it is shown that the H implantation has a catalyzing effect on the etching, allowing the removal of horizontal SiN surface with almost infinite selectivity over vertical surface. This work shows that the concept that we propose is very promising for the development of highly area selective etching processes. This work was financially supported by the LabEx Minos ANR-10-LABX-55-01 and the French RENATECH network and technically supported by AMAT France and AMAT USA [1] S. Natarajan et al., “A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size,” in IEDM Tech. Dig., pp. 3.7.1–3.7.3 (2014). [2] P. Zheng, D. Connelly, F. Ding, and T.-J. King Liu, IEEE Trans. Elec. Dev., 62, NO. 12, 3945 (2015) [3] F. S. Minaye Hashemi, B. R. Birchansky, and S. F. Bent, “Selective Deposition of Dielectrics: Limits and Advantages of Alkanethiol Blocking Agents on Metal−Dielectric Patterns” Appl. Mater. Interfaces 2016, 8, 33264−33272 [4] W-H Kim, F. Sadat Minaye Hashemi, A. J. M. Mackus, J. Singh, Y. Kim, D Bobb-Semple, Y. Fan, T. Kaufman-Osborn, L. Godet, and S. F. Bent, A Process for Topographically Selective Deposition on 3D Nanostructures by Ion Implantation ACS Nano 2016, 10, 4451−4458 Figure 1
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May 4, 2020
Jing Zhang + 5
Open Access