BJT Structure Research Articles

An analytical model for the body contact current of PDSOI nMOSFETs

The impact ionization of pinch-off region and the parasitic BJT structure are considerable issues for PDSOI nMOSFETs at high drain voltage bias. The measured body contact current can reflect both two mechanisms. An analytical model with impact ionization and parasitic BJT considered are proposed in this work for the body contact current modeling. This model is presented as an equivalent circuit and 5 joint nonlinear equations. The fixed-point method is applied to solve these joint equations and a graphical C++ Qt based software are developed for the model parameters extraction. The validity and accuracy of model are verified by the PDSOI nMOSFET of 130 nm process node. This model is meaningful for the electrical behavior prediction of PDSOI nMOSFETs with large external bias range.

A Gated-Diode ESD SCR-Incorporated BJT for Reversed Floating P⁺ Junction Modulation

This work presents a novel gated- diode SCR-incorporated BJT (SIB) structure for ESD protection purpose. A gated diode built in the SIB structure modulates reverse-biased P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> / N-well diode for better junction breakdown control. This device could achieve high TLP second breakdown current /ESD threshold close to that of an SCR, very high holding voltage, and reduced trigger voltage, as well as excellent latchup immunity.

Simulation study of a 4H-SiC lateral BJT for monolithic power integration * * Project supported by the National Natural Science Foundation of China (No. 51577054).

Power integration based on 4H-SiC is a very promising technology for high-frequency and high-temperature power electronics applications. However, the fabrication processes used in Si BiCMOS technology is not applicable in 4H-SiC at present, and few studies on the monolithic power integration of the SiC signal devices and power devices have been reported. In this paper, we propose a novel lateral BJT structure, which is suitable for monolithically integrating with the vertical power BJT on the same epitaxial wafer at the cost of one additional mask. The signal BJT’s static and dynamic characteristics are comprehensively investigated by TCAD simulation. Simulation results show that the common-emitter current gains of the 4H-SiC signal BJT are 133 and 52 at room temperature and 300 °C, respectively. Its implementation in an inverter shows that its switching time is about 200 ns.

A High Current Gain 4H-SiC BJT of Novel Epitaxial Passivation Structure

This paper proposes a novel high-gain 4H-SiC BJT structure with a p-type epitaxial layer on top of the extrinsic base layer. The current gain of the novel structure is improved by 140% compared with the conventional one by the simulator tool with the number of reasonable interface traps, which could be ascribed to the epitaxial layer to reduce the surface recombination in the extrinsic base. The process to fabricate this structure is also proposed in the paper.

Обобщенная TCAD-модель для учета радиационных эффектов в структурах МОП и биполярных транзисторов

Обобщенная TCAD-модель для учета радиационных эффектов в структурах МОП и биполярных транзисторов

A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process

A variety of smart imaging and neuromorphic applications perform time-domain image acquisition in order to imitate biological systems and reduce the growing transmission bandwidth of the modern imaging devices. Because they operate in time-domain, they require the highest possible pixel responsivity and response speed. This work provides a comparative experimental study of different unconventional photodetecting structures with respect to these parameters. Several on-chip photodetecting device structures are designed using a low-cost standard 0.18μm CMOS process. The comparison in terms of measured quantum efficiency, light responsivity and the response speed is presented between conventional and comb-shaped N-well/P-substrate photodiodes, conventional and comb-shaped, vertical and lateral photo-bipolar-junction-transistors (photo-BJTs) and a Darlington pair of bipolar-junction phototransistors. The photodetectors are embedded in a conventional three transistor active pixel topology and measured using a customized low-cost measurement setup. The pixel quantum efficiency, responsivity and response speed are measured for each structure and the results are presented in detail. The obtained results demonstrate the benefits of using standard-CMOS-compatible BJT structures in time-domain applications. The BJT-based photodetectors show increased responsivity to green–yellow light region (500–600nm wavelength) compared to conventional N-well/P-substrate diode. The highest responsivity is achieved by a combination of lateral and vertical BJT. The fastest response is achieved by the rarely used Darlington pair configuration of BJTs, which demonstrates the potential benefit of using this structure for time-domain imaging applications. A low-cost measurement setup and the measurement methodology are described in detail to make the experiment reproducible for any other standard CMOS process.

Novel PNP BJT Structure to Improve Matching Characteristics for Analog and Mixed Signal Integrated Circuit Applications

Novel PNP BJT Structure to Improve Matching Characteristics for Analog and Mixed Signal Integrated Circuit Applications

Electron transport in thin-base transistor structures exposed to high-energy photons

Monte Carlo simulations are run to investigate the electron transport in thin-base BJT structures exposed to high-energy photons. The radiation-induced distortion of the electron energy distribution function is shown to be capable of changing, in either direction, the rate of impact ionization in the collector depletion layer to a great extent.

2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI

We report a novel BiCMOS compatible lateral SiC N-emitter, SiGe P-base Schottky metal-collector NPM HBT on SOI. The proposed lateral NPM HBT performance has been evaluated in detail using 2-dimensional device simulation by comparing it with the equivalent NPN HBT and homojunction silicon NPM BJT structures. Based on our simulation results, it is observed that while both the lateral NPM and NPN HBTs exhibit high current gain, high cut-off frequency compared to the homojunction NPN BJT, the lateral NPM HBT has the additional benefit of suppressed Kirk effect and excellent transient response over its counterpart lateral NPN HBT. The improved performance of the proposed NPM HBT is discussed in detail and a CMOS compatible process is suggested for its fabrication.

A simple, high performance TFSOI complementary BiCMOS technology for low power wireless applications

The authors describe a simple, high performance thin-film silicon-on-insulator (TFSOI) complementary BiCMOS (C-BiCMOS) technology, which can be used in low power wireless communication applications. In this technology, a novel, high performance lateral BJT structure is implemented using a gate spacer to obtain a thin base width and a minimum base linkage to the external base for minimized base resistance. A lateral NPN transistor (with maximum oscillation frequency (f/sub max/) of 29 GHz, cut-off frequency (f/sub T/) of 8 GHz, current gain (h/sub FE/) of 78, and collect-emitter breakdown voltage with base open (BV/sub CEO/) of 5 V), a lateral PNP transistor (h/sub FE/ of 51 and BV/sub CEO/ of 4.5 V), and NMOS and PMOS transistors (0.5 /spl mu/m channel length and 5 /spl mu/m channel width, 0.5/-0.8 V threshold voltage) am fabricated. This technology provides very promising low power, low cost, and high performance solutions for RF mixed-signal system-on-a-chip (SoC) applications.

Shallow buried channel gated BJT on TFSOI substrate

The gated BJT structure is inherently suitable for SOI BiCMOS technology. However, being a surface channel device, it suffers higher noise and degraded carrier transport. In this study, a novel shallow buried channel design on TFSOI is proposed. Devices with various geometries have been fabricated with a simple CMOS-compatible process. These devices have low turn-on voltage, ideal BJT I-V characteristics with current gain higher than 1000, and a maximum transconductance of 290 mS/mm for a 0.5 /spl mu/m channel length and 15 nm gate oxide. Careful measurements show that an order of magnitude improvement in noise performance can be expected from the buried channel operation. These devices are suitable for various BiCMOS applications. >