Memory Bits Research Articles

Efficient Convex Optimization Requires Superlinear Memory

We show that any memory-constrained, first-order algorithm which minimizes d -dimensional, 1-Lipschitz convex functions over the unit ball to 1/poly( d ) accuracy using at most d 1.25 - δ bits of memory must make at least \(\tilde{\Omega }(d^{1 + (4/3)\delta })\) first-order queries (for any constant \(\delta \in [0, 1/4]\) ). Consequently, the performance of such memory-constrained algorithms are at least a polynomial factor worse than the optimal Õ( d ) query bound for this problem obtained by cutting plane methods that use Õ(d 2 ) memory. This resolves one of the open problems in the COLT 2019 open problem publication of Woodworth and Srebro.

Strategy Complexity of Reachability in Countable Stochastic 2-Player Games

AbstractWe study countably infinite stochastic 2-player games with reachability objectives. Our results provide a complete picture of the memory requirements of $$\varepsilon $$ ε -optimal (resp. optimal) strategies. These results depend on the size of the players’ action sets and on whether one requires strategies that are uniform (i.e., independent of the start state). Our main result is that $$\varepsilon $$ ε -optimal (resp. optimal) Maximizer strategies requires infinite memory if Minimizer is allowed infinite action sets. This lower bound holds even under very strong restrictions. Even in the special case of infinitely branching turn-based reachability games, even if all states allow an almost surely winning Maximizer strategy, strategies with a step counter plus finite private memory are still useless. Regarding uniformity, we show that for Maximizer there need not exist memoryless (i.e., positional) uniformly $$\varepsilon $$ ε -optimal strategies even in the special case of finite action sets or in finitely branching turn-based games. On the other hand, in games with finite action sets, there always exists a uniformly $$\varepsilon $$ ε -optimal Maximizer strategy that uses just one bit of public memory.

Reversing the magnetization of 50-nm-wide ferromagnets by ultrashort magnons in thin-film yttrium iron garnet.

Spin waves (magnons) can enable neuromorphic computing by which one aims at overcoming limitations inherent to conventional electronics and the von Neumann architecture. Encoding magnon signal by reversing magnetization of a nanomagnetic memory bit is pivotal to realize such novel computing schemes efficiently. A magnonic neural network was recently proposed consisting of differently configured nanomagnets that control nonlinear magnon interference in an underlying yttrium iron garnet (YIG) film [Papp et al., Nat. Commun., 2021, 12, 6422]. In this study, we explore the nonvolatile encoding of magnon signals by switching the magnetization of periodic and aperiodic arrays (gratings) of Ni81Fe19 (Py) nanostripes with widths w between 50 nm and 200 nm. Integrating 50-nm-wide nanostripes with a coplanar waveguide, we excited magnons having a wavelength λ of ≈100 nm. At a small spin-precessional power of 11 nW, these ultrashort magnons switch the magnetization of 50-nm-wide Py nanostripes after they have propagated over 25 μm in YIG in an applied field. We also demonstrate the magnetization reversal of nanostripes patterned in an aperiodic sequence. We thereby show that the magnon-induced reversal happens regardless of the width and periodicity of the nanostripe gratings. Our study enlarges substantially the parameter regime for magnon-induced nanomagnet reversal on YIG and is important for realizing in-memory computing paradigms making use of magnons with ultrashort wavelengths at low power consumption.

Accelerating the neural network controller embedded implementation on FPGA with novel dropout techniques for a solar inverter

Accelerating neural network (NN) controllers is important for improving the performance, efficiency, scalability, and reliability of real-time systems, particularly in resource-constrained embedded systems. This paper introduces a novel weight-dropout method for training neural network controllers in real-time closed-loop systems, aimed at accelerating the embedded implementation for solar inverters. The core idea is to eliminate small-magnitude weights during training, thereby reducing the number of necessary connections while ensuring the network’s convergence. To maintain convergence, only non-diagonal elements of the weight matrices were dropped. This dropout technique was integrated into the Levenberg–Marquardt and Forward Accumulation Through Time algorithms, resulting in more efficient training for trajectory tracking. We executed the proposed training algorithm with dropout on the AWS cloud, observing a performance increase of approximately four times compared to local execution. Furthermore, implementing the neural network controller on the Intel Cyclone V Field Programmable Gate Array (FPGA) demonstrates significant improvements in computational and resource efficiency due to the proposed dropout technique leading to sparse weight matrices. This optimization enhances the suitability of the neural network controller for embedded environments. In comparison to Sturtz et al. (2023), which dropped 11 weights, our approach eliminated 18 weights, significantly boosting resource efficiency. This resulted in a 16.40% reduction in Adaptive Logic Modules (ALMs), decreasing the count to 47,426.5. Combinational Look-Up Tables (LUTs) and dedicated logic registers saw reductions of 17.80% and 15.55%, respectively. However, the impact on block memory bits is minimal, showing only a 1% improvement, indicating that memory resources are less affected by weight dropout. In contrast, the usage of Memory 10 Kilobits (MK10s) dropped from 97 to 87, marking a 10% improvement. We also propose an adaptive dropout technique to further improve the previous results.

Mathematical analysis of spin transport in topological insulators to optimize memory devices performance using numerical simulations

Understanding spin transport in topological insulators (TIs) is crucial for the development of spin-based technologies, such as magnetic memory, sensors, and quantum bits. To optimize memory device performance, we developed a comprehensive mathematical model that describes the evolution of spin density, as a function of space and time, taking into account spin-momentum locking, spin-orbit coupling, spin dynamics, and diffusive transport processes (including phonon and impurity scattering). Using numerical simulations (finite element method and Backward Euler Method) implemented in Python, we analyzed the spin transport in TIs. Our study demonstrated a critical dependence of spin transport efficiency on device length, with a maximum efficiency of 75% at a length of 8 micrometers. Beyond a critical length of 10 micrometers, efficiency recovered, reaching 80% at 14 micrometers. We observed oscillatory behavior in spin polarization, with amplitude modulation indicating constructive and destructive interference patterns. The inclusion of spin-orbit coupling and Dirac terms in our model revealed a non-uniform spin polarization distribution, with a 30% increase in polarization near the center. Defects and boundaries significantly impacted spin transport, reducing polarization by 40% near the defect region. Through optimization, we achieved a 25% increase in spin transport efficiency and a 20% enhancement in memory device performance. Our results demonstrate the crucial role of optimizing device length, material quality, and interface engineering in achieving efficient spin transport and improved memory device performance, paving the way for the development of high-performance spin-based technologies.

Resource efficient stabilization for local tasks despite unknown capacity links

Self-stabilizing protocols enable distributed systems to recover correct behavior starting from any arbitrary configuration. In particular, when processors communicate by message passing and the communication links are unbounded, fake messages may be placed in communication links by an adversary. When the number of such fake messages is unknown, self-stabilization may require huge resources:•generic solutions (a.k.a. data link protocols) require unbounded resources, which makes them unrealistic to deploy,•specific solutions (e.g., census or tree construction) require O(nlog⁡n) or O(Δlog⁡n) bits of memory per node, where n denotes the network size and Δ its maximum degree, which may prevent scalability.We investigate the possibility of resource-efficient self-stabilizing protocols in this context.Specifically, we present self-stabilizing protocols for (Δ+1)-coloring and maximal independent set construction in any n-node graph, under the asynchronous message-passing model. The problems of (Δ+1)-coloring and maximal independent set construction are widely regarded as benchmark problems for evaluating local algorithms. Our protocols offer many desirable features. They are deterministic, converge in O(kΔn2log⁡n) message exchanges, where k is the (unknown) initial number of (possibly corrupted) messages in a communication link. They use messages of O(log⁡log⁡n+log⁡Δ) bits with a memory of O(Δlog⁡Δ+log⁡log⁡n) bits at each node. The resource consumption of our protocols is thus almost oblivious to the number of nodes, enabling scalability. Moreover, a striking property of our protocols is that the nodes do not need to know the number, or any bound on the number of messages initially present in each communication link of the initial (potentially corrupted) network configuration. This permits our protocols to handle any future network with unknown message capacity communication links.A key building block of our coloring and maximal independent set schemes is an algorithm to obtain an acyclic orientation of graph edges, that is of independent interest, and can serve as a useful tool for solving other tasks in this challenging setting.

Parameterized Complexity of Streaming Diameter and Connectivity Problems

We initiate the investigation of the parameterized complexity of Diameter and Connectivity in the streaming paradigm. On the positive end, we show that knowing a vertex cover of size k allows for algorithms in the Adjacency List (AL) streaming model whose number of passes is constant and memory is O(logn)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(\\log n)$$\\end{document} for any fixed k. Underlying these algorithms is a method to execute a breadth-first search in O(k)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(k)$$\\end{document} passes and O(klogn)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(k \\log n)$$\\end{document} bits of memory. On the negative end, we show that many other parameters lead to lower bounds in the AL model, where Ω(n/p)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\Omega (n/p)$$\\end{document} bits of memory is needed for any p-pass algorithm even for constant parameter values. In particular, this holds for graphs with a known modulator (deletion set) of constant size to a graph that has no induced subgraph isomorphic to a fixed graph H, for most H. For some cases, we can also show one-pass, Ω(nlogn)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\Omega (n \\log n)$$\\end{document} bits of memory lower bounds. We also prove a much stronger Ω(n2/p)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\Omega (n^2/p)$$\\end{document} lower bound for Diameter on bipartite graphs. Finally, using the insights we developed into streaming parameterized graph exploration algorithms, we show a new streaming kernelization algorithm for computing a vertex cover of size k. This yields a kernel of 2k vertices (with O(k2)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(k^2)$$\\end{document} edges) produced as a stream in poly(k)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {poly}(k)$$\\end{document} passes and only O(klogn)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(k \\log n)$$\\end{document} bits of memory.

Graphene–fullerene heterostructures as robust and flexible nanomechanical bits

Electrical computers have revolutionized society over the past several decades, but questions have remained about their ability to perform in extreme environments, such as their stability at high-temperature conditions. This has motivated the recent surge of interest in developing mechanical computing platforms at all length scales, including the nanoscale, in which traditional electrical computers are augmented with mechanical ones. However, the most proposed nanomechanical bits are volatile memory bits based on the dynamic response of nanomechanical resonators, and as such, there is a need to develop robust and reprogrammable entirely non-volatile nanomechanical bits. Here, we exploit the multiple quasi-stable configurations of the graphene/fullerene/graphene (GFG) van der Waals heterostructure to work as a novel nonvolatile nanomechanical bit. The GFG heterostructure is unique and robust in that it can return to its initial state without further mechanical input, it can be used for logic functions at relevant operating temperatures through simple application of uniaxial strain, it can exhibit reprogrammability between five basic logic gates (NOT, AND, NAND, OR, NOR) by varying the magnitude or direction of applied strain, and it can be used to represent combinatorial logic through full and half adders. These findings provide a new opportunity to develop mechanical computers based on the large class of nanomaterials.

Time delay reservoir computing with a silicon microring resonator and a fiber-based optical feedback loop

Silicon microring resonators serve as critical components in integrated photonic neural network implementations, owing to their compact footprint, compatibility with CMOS technology, and passive nonlinear dynamics. Recent advancements have leveraged their filtering properties as weighting functions, and their nonlinear dynamics as activation functions with spiking capabilities. In this work, we investigate experimentally the linear and nonlinear dynamics of microring resonators for time delay reservoir computing, by introducing an external optical feedback loop. After effectively mitigating the impact of environmental noise on the fiber-based feedback phase dependencies, we evaluate the computational capacity of this system by assessing its performance across various benchmark tasks at a bit rate of few Mbps. We show that the additional memory provided by the optical feedback is necessary to achieve error-free operation in delayed-boolean tasks that require up to 3 bits of memory. In this case the microring was operated in the linear regime and the photodetection was the nonlinear activation function. We also show that the Santa Fe and Mackey Glass prediction tasks are solved when the microring nonlinearities are activated. Notably, our study reveals competitive outcomes even when employing only 7 virtual nodes within our photonic reservoir. Our findings illustrate the silicon microring’s versatile performance in the presence of optical feedback, highlighting its ability to be tailored for various computing applications.

Evidence of 3D Topological-Domain Dynamics in KTN:Li Polarization-Supercrystal Formation.

We experimentally and theoretically investigate thermal domain evolution in near-transition KTN:Li. Results allow us to establish how polarization supercrystals form, a hidden 3D topological phase composed of hypervortex defects. These are the result of six converging polarization vortices, each associated to one orientation of the 3D broken inversion symmetry. We also identify rescaling soliton lattices and domain patterns that replicate on different scales. Findings shed light on volume domain self-organization into closed-flux patterns and open up new scenarios for topologically protected noise-resistant ferroelectric memory bits.

Design methodology of compact edge vision transformer CiM considering non-volatile memory bit precision and memory error tolerance

This paper proposes a design methodology for a compact edge vision transformer (ViT) Computation-in-Memory (CiM). ViT has attracted much attention for its high inference accuracy. However, to achieve high inference accuracy, the conventional ViT requires fine-tuning many parameters with pre-trained models on large datasets and a large number of matrix multiplications in inference. Thus, to map ViT to non-volatile memory (NVM)-based CiM compactly for edge applications (IoT/Mobile devices) in inference, this paper analyses fine-tuning in training, clipping, and quantization in inference. The proposed compact edge ViT CiM can be optimized by three design methods according to use cases considering the required fine-tuning time, ease of setting memory bit precision, and memory error tolerance of ViT CiM. As a result, in CIFAR-10, the most compact type successfully reduces the total memory size of ViT by 85.8% compared with the conventional ViT. Furthermore, the high accuracy type and high error-tolerant type improve inference accuracy by 4.4% and memory-error tolerance by more than four times compared with convolutional neural networks, respectively.

Stability Parameters of Register File Bit Cell with Low Power Consumption Priority

This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

Design of Convolutional Neural Networks Architecture for Non-Profiled Side-Channel Attack Detection

Deep learning (DL) is a new option that has just been made available for side-channel analysis. DL approaches for profiled side-channel attacks (SCA) have dominated research till now. In this attack, the attacker has complete control over the profiling device and can collect many traces for a range of critical parameters to characterise device leakage before the attack. In this study, we apply DL algorithms to non-profiled data. An attacker can only retrieve a limited number of side-channel traces from a closed device with an unknown key value in non-profiled mode. The authors conducted this research. Key estimations and deep learning measurements can reveal the secret key. We prove that this is doable. This technology is excellent for non-profits. DL and neural networks can benefit these organisations. Neural networks can provide a new technique to verify the safety of hardware cryptographic algorithms. It was recently suggested. This study creates a non-profiled SCA utilising convolutional neural networks (CNNs) on an AVR microcontroller with 8 bits of memory and the AES-128 cryptographic algorithm. We used aligned power traces with several samples to demonstrate how challenging CNN-based SCA is in practise. This will help us reach our goals. Here is another technique to create a solid CNN data set. In particular, CNN-based SCA experiment data and noise effects are examined. These experiments employ power traces with Gaussian noise. The CNN-based SCA works well with our data set for non-profiled attacks. Gaussian noise on power traces causes many more issues. These results show that our method can recover more bytes successfully from SCA compared to other methods in correlation power analysis (CPA) and DL-SCA without regularisation.

The Space Complexity of Sum Labelling

A graph is called a sum graph if its vertices can be labelled by distinct positive integers such that there is an edge between two vertices if and only if the sum of their labels is the label of another vertex of the graph. Most papers on sum graphs consider combinatorial questions like the minimum number of isolated vertices that need to be added to a given graph to make it a sum graph. In this paper, we initiate the study of sum graphs from the viewpoint of computational complexity. Notice that every n-vertex sum graph can be represented by a sorted list of n positive integers where edge queries can be answered in mathscr {O}(log n) time. Therefore, upper-bounding the numbers used as vertex labels also upper-bounds the space complexity of storing the graph in the database. We show that every n-vertex, m-edge, d-degenerate graph can be made a sum graph by adding at most m isolated vertices to it, such that the largest numbers used as vertex labels grows as mathscr {O}(n^2d). This enables us to store the graph using mathscr {O}(mlog n) bits of memory. For sparse graphs (graphs with mathscr {O}(n) edges), this matches the trivial lower bound of Omega (nlog n). As planar graphs and forests have constant degeneracy, our result implies an upper bound of mathscr {O}(n^2) on their label numbers. The previously best known upper bound on the numbers needed for labelling general graphs with the minimum number of isolated vertices was mathscr {O}(4^n), due to Kratochvíl, Miller & Nguyen (2001). Furthermore, their proof was existential, whereas our labelling can be constructed in polynomial time.

Radiation hardened 11T memory cell for space applications

Continuous nanometer technology scaling, along with rapid growth in the field of artificial intelligence (AI), internet-of-things (IoT), and other high-performance computing applications increases the need for low power and soft error immune VLSI circuits. Conventional radiation hardened bit cell such as QUATRO10T with partial single event upset (SEU) immunity and bit cells such as DICE12T, WE-QUATRO12T, and RHD13T needs large area and power consumption. To address these problems, a soft error immune radiation hardened memory cell 11T (RHMC11T) static random-access memory (SRAM) bit cell is proposed which is immune to both SEU and single event multiple node upsets (SEMNU) along with good read and write stability. The enhancement in the key parameters of the proposed cell is confirmed by comparing the proposed bit cell with the conventional bit cells such as 6T, NS10T, PS10T, QUATRO10T, RHMD10T, RHBD10T, 11T, and 12T. The critical charge of the proposed RHMC11T is improved by 43%, 27%, 19%, 2%, 2%, and 4% while comparing with 6T, NS10T, PS10T, QUATRO10T, RHBD10T, and 11T. The proposed bit cell has higher SVNM of 49%, 19%, 11%, 8%, and 5% and smaller WTV of 50%, 33%, 23%, 18%, and 21% compared to 6T, PS10T, RHMD10T, RHBD10T, and 12T respectively. The proposed RHMC11T has lesser read access time of 63%, 50%, 46%, 6%, and 6% compared to NS10T, PS10T, QUATRO10T, RHMD10T, and 11T. The proposed RHMC11T bit cell with dedicated write and read word lines makes it applicable for bit interleaving architecture and also it satisfies reliability requirements making it a good choice for highly radiative terrestrial environment applications such as in aerospace and satellites.

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K

In this work, we are the first to investigate and model the characteristics of a commercial 5nm FinFET technology from room temperature (300K) all the way down to cryogenic temperature (10K). We focus on SRAM circuits demonstrating how cryogenic temperatures impact their power, delay, and reliability. SRAM memories are key components in quantum read-out and control circuits, and therefore characterizing their key figure of merits when building cryogenic-CMOS circuits is essential. To achieve that, we first measure the electrical characteristics of nFinFET and pFinFET devices from 300K down to 10K. Then, we carefully calibrate the cryogenic-aware BSIM-CMG, which is the first industry-standard compact model for FinFET technologies designed for cryogenic temperatures. This enables us to reproduce the experimental data in which SPICE simulations come with an excellent agreement with the measurements. Using our well-calibrated transistor models, we simulate a complete 32-bit SRAM memory array, including a write driver, sense amplifier, pre-charger, and output latch. Then, we investigate how cryogenic temperatures impact the SRAM read and write delays at several stages during the operation, as well as the power and energy. For a more comprehensive analysis, we perform our studies for different SRAM types covering high-density, high-performance, and low-voltage cells. All transistor and SRAM analyses are performed at both room temperature and cryogenic temperature to obtain detailed comparisons revealing the exact role that cryogenic temperature plays in SRAMs. All in all, we demonstrate that commercial 5nm FinFET is indeed suitable for cryogenic-CMOS circuits required in quantum processors, revealing that the performance of SRAMs at 10K does improve while power and energy consumption are reduced. Nevertheless, SRAM reliability is more challenging in which noise margins need to be carefully engineered to remain sufficient at 10K.

Memory optimal dispersion by anonymous mobile robots

Consider a team of k≤n autonomous mobile robots initially placed at a node of an arbitrary graph G with n nodes. The dispersion problem asks for a distributed algorithm that allows the robots to reach a configuration in which each robot is at a distinct node of the graph. If the robots are anonymous, i.e., they do not have any unique identifiers, then the problem is not solvable by any deterministic algorithm. However, the problem can be solved even by anonymous robots if each robot is given access to a fair coin which they can use to generate random bits. In this setting, it is known that the robots require Ω(logΔ) bits of memory to achieve dispersion, where Δ is the maximum degree of G. On the other hand, the best known memory upper bound is min{Δ,max{logΔ,logD}} (D = diameter of G), which can be ω(logΔ), depending on the values of Δ and D. In this paper, we close this gap by presenting an optimal algorithm requiring O(logΔ) bits of memory.

Computationally efficient GPU based NS solver for two dimensional high-speed inviscid and viscous compressible flows

In this study, we proposed a novel GPU-based solution for modelling two-dimensional inviscid and viscous compressible supersonic/hypersonic flows. Texture and surface pointers are used to access GPU memory locations. For effective and efficient use of surface pointers, we grouped multiple 2D arrays referenced and indexed by a single 3D surface pointer. To enable the proposed solver for double-precision calculations, two consecutive 32-bit memory locations were grouped to maintain the efficiency of surface pointers while taking advantage/accuracy of 64-bit calculations. Resolving data and computation dependencies for parallel applications is another complex task that is the focus of this study. Computation dependencies have been solved by using multiple mutually synchronized GPU kernels and executing them sequentially using the GPU default stream to ensure that all relevant data is available to the threads or computed before they actually use it. Consequently, there is no intra-core data dependency in our proposed approach, while inter-core data dependency is successfully solved by stringing multiple kernels together. Using NVIDIA GTX 660 GPUs, we achieved 20x speedup compared to traditional Core i5® computers. This speedup is the result of the Surface Pointer's GPU capabilities for double precision computations. The simulation results are also consistent with the experimental and numerical results of this study.

Noise–dissipation relation for nonlinear electronic circuits

An extension of fluctuation–dissipation theorem is used to derive a “speed limit” theorem for nonlinear electronic devices. This speed limit provides a lower bound on the dissipation that is incurred when transferring a given amount of electric charge in a certain amount of time with a certain noise level (average variance of the current). This bound, which implies a high energy dissipation for fast, low-noise operations (such as switching a bit in a digital memory), brings together recent results of stochastic thermodynamics into a form that is usable for practical nonlinear electronic circuits, as we illustrate on a switching circuit made of an nMOS pass gate in a state-of-the-art industrial technology.

Pneumatic computers for embedded control of microfluidics.

Alternative computing approaches that interface readily with physical systems are well suited for embedded control of those systems. We demonstrate finite state machines implemented as pneumatic circuits of microfluidic valves and use these controllers to direct microfluidic liquid handling procedures on the same chip. These monolithic integrated systems require only power to be supplied externally, in the form of a vacuum source. User input can be provided directly to the chip by covering pneumatic ports with a finger. State machines with up to four bits of state memory are demonstrated, and next-state combinational logic can be fully reprogrammed by changing the hole-punch pattern on a membrane in the chip. These pneumatic computers demonstrate a framework for the embedded control of physical systems and open a path to stand-alone lab-on-a-chip devices capable of highly complex functionality.