Bitonic Sort Research Articles

Minimizing communication in the bitonic sort

This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an /spl Omega/-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log/sup 2/ N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network.

An optimal hardware-algorithm for sorting using a fixed-size parallel sorting device

We present a hardware-algorithm for sorting N elements using either a p-sorter or a sorting network of fixed I/O size p while strictly enforcing conflict-free memory accesses. To the best of our knowledge, this is the first realistic design that achieves optimal time performance, running in /spl Theta/(NlogN/plogp) time for all ranges of N. Our result completely resolves the problem of designing an implementable, time-optimal algorithm for sorting N elements using a p-sorter. More importantly, however, our result shows that, in order to achieve optimal time performance, all that is needed is a sorting network of depth O(log/sup 2/p) such as, for example, Batcher's classic bitonic sorting network.

Realization of large-scale distributors based on Batcher sorters

We rigorously examine how to construct a large-scale distributor by taking a logical and systematic approach. We first consider requirements for realization, which include the independent operation of unit modules and the packet sequence integrity, and consider what kind of existing devices have large-scale growth potential. In this process, we take the Batcher sorting network as the candidate device and show that the distribution function can be incorporated to it by furnishing each constituent sorting element with the state inversion capability. Then we show that this is equivalent to replacing each sorting element with a 2/spl times/2 distributor. As a consequence, the large-scale distributor design problem turns into a simple substitution problem for which we substitute a unit distributor for each sorting element in the prototype Batcher sorting network. In addition, we show that this substitution approach can be extended to larger scale unit distributor modules, thus enabling a large-scale distributor realization. The resulting large-scale distributor design procedure can be summarized as follows: given a desired size L=MN for the design of a large-scale distributor, we first design an N/spl times/N Batcher sorter (BS) and then replace each constituent 2/spl times/2 sorting element with a 2M/spl times/2M distributor module.

Parallel multiplication using fast sorting networks

A recent paper describes the use of Svoboda's binary counter in the construction of fast parallel multipliers. The resulting approach was shown to be faster than the conventional Dadda multiplier when the wordlength N was small. Unfortunately, the growth in the number of gates of that method was O(N/sup 3/) and the speed was O(N). In this paper, Batcher's bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is O(N/sup 2/ log/sup 2/ N), and the speed is O(log/sup 2/ N).

ATM switching by divide-and-conquer interconnection of partial sorters

This article presents the construction of a family of ATM switching fabrics to be used as generic components in ATM switching. Such a component absorbs the output contention problem and traffic burtiness without requiring centrally controlled routing, preprocessing of input traffic, or packet buffering. One application is to serve as the main module in a large self-route switch core. The construction is by the deployment of a partial sorter in place of every routing cell in a banyan-type routing network. In order to partition the large fabric into a generic component of the chip size and also to optimize the layout, the specific choice of the underlining banyan-type network is a divide-and-conquer network. Meanwhile, partial sorters are constructed by the k-sorting algorithm, which unifies and generalizes the classical algorithms of binary merge exchange, bitonic sorting, and odd–even merge exchange.

K-bitonic sort

Ak-bitonic sort which generalizes the bitonic sort is proposed. The theorem of the bitonic sort, which merges two monotonic sequences into one order sequence, is extended into the theorem ofk-bitonic sort. Thek-bitonic sort merges (K (=2k or 2k−1) monotonic sequences into one order sequence in\(\left\lceil {log_2 K} \right\rceil \left\lceil {log_2 N} \right\rceil - \tfrac{{\left\lceil {log_2 K} \right\rceil (\left\lceil {log_2 K} \right\rceil - 1)}}{2}\) steps, where\(k = \left\lceil {\tfrac{K}{2}} \right\rceil \) is an integer andk≥1. Thek-bitonic sort is the Batcher's bitonic sort whenk=1.

Asymptotics of Divide-and-Conquer Recurrences: Batcher's Sorting Algorithm and a Minimum Euclidean Matching Heuristic

We examine in detail the asymptotic behaviors of the number of comparisons used in Batcher's sorting algorithm and a quantity arising in analyzing the rectangle heuristic for finding minimum Euclidean matching due to Supowit and Reingold. We put forth methods (elementary and analytic) for computing the Fourier coefficients of periodic functions appearing in the asymptotic expansions of these quantities. The methods consist of the approach by Flajolet and Golin for divide-and-conquer recurrences and van der Corput's method from analytic number theory for exponential sums.

Performance of fault-tolerant sorting network for ATM switching

This paper proposes a self-routing fault-tolerant sorting network that employs an enhanced scheme of the Batcher sorting network. It consists of two Batcher sorting planes with links provided at every stage to allow cell transfer to and from each sorting network, thereby offering multiple paths between each input-output pair and giving a high degree of fault-tolerance and overcoming the single path limitation of the Batcher sorting network. The proposed fault-tolerant sorting network offers high fault-tolerance; low and fixed amount of delay; maintenance of cell sequence; simple routing; and regularity and modularity. Expressions for reliability, mean time to failure, and availability are derived and the numerical results show that the proposed fault-tolerant sorting network has superior performance as compared to Batcher and parallel Batcher sorting networks. Using simulations, we have shown that the proposed fault-tolerant sorting network has a high probability of survival under a faulty environment.

Optoelectronic systems based on InGaAs–complementary-metal-oxide-semiconductor smart-pixel arrays and free-space optical interconnects

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batcher's bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.

An Experimental Analysis of Parallel Sorting Algorithms

We have developed a methodology for predicting the performance of parallel algorithms on real parallel machines. The methodology consists of two steps. First, we characterize a machine by enumerating the primitive operations that it is capable of performing along with the cost of each operation. Next, we analyze an algorithm by making a precise count of the number of times the algorithm performs each type of operation. We have used this methodology to evaluate many of the parallel sorting algorithms proposed in the literature. Of these, we selected the three most promising, Batcher's bitonic sort, a parallel radix sort, and a sample sort similar to Reif and Valiant's flashsort, and implemented them on the connection Machine model CM-2. This paper analyzes the three algorithms in detail and discusses the issues that led us to our particular implementations. On the CM-2 the predicted performance of the algorithms closely matches the observed performance, and hence our methodology can be used to tune the algorithms for optimal performance. Although our programs were designed for the CM-2, our conclusions about the merits of the three algorithms apply to other parallel machines as well.

A technique for overlapping computation and communication for block recursive algorithms

SUMMARY This paper presents a design methodology for developing efficient distributed-memory parallel programs for block recursive algorithms such as the fast Fourier transform (FFT) and bitonic sort. This design methodology is specifically suited for most modern supercomputers having a distributed-memory architecture with a circuit-switched or wormhole routed mesh or a hypercube interconnection network. A mathematical framework based on the tensor product and other matrix operations is used for representing algorithms. Communication-efficient implementations with effectively overlapped computation and communication are achieved by manipulating the mathematical representation using the tensor product algebra. Performance results for FFT programs on the Intel Paragon are presented. ©1998 John Wiley & Sons, Ltd.

Some topological properties of bitonic sorters

The paper proves some topological properties of bitonic sorters, which have found applications in constructing, along with banyan networks, internally nonblocking switching fabrics in future broadband networks. The states of all the sorting elements of an N/spl times/N bitonic sorter are studied for four different input sequences {a/sub i/}/sub i=l//sup N/, {b/sub i/}/sub i=l//sup N/, {c/sub i/}/sub i=l//sup N/, and {d/sub i/}/sub i=l//sup N/ where a/sub i/=i-1, b/sub i/=N-i, and the binary representations of c/sub i/ and d/sub i/ are the bit reverse of those of a/sub i/ and b/sub i/, respectively. An application of these topological properties is to help design efficient fault diagnosis procedures. We present an example for detecting and locating a single faulty sorting element under a simple fault model where all sorting elements are always in the straight state or the cross state.

Design, analysis, and evaluation of concurrent checking sorting networks

In this brief, we propose two new concurrent error-detection (CED) schemes for a class of sorting networks, e.g., odd-even transposition, bitonic, and perfect shuffle sorting networks. A probabilistic method is developed to analyze the fault coverage, and the hardware overhead is evaluated. We first propose a CED scheme by which all errors caused by single faults in a concurrent checking sorting network can be detected. This scheme is the first one available to use significantly less hardware overhead than duplication without compromising throughput. From this scheme, we develop another fault detection scheme which sharply reduces the hardware overhead (using an additional 10%/spl sim/30% hardware) but still achieves virtually 1001 fault coverage.

Performance modelling of three parallel sorting algorithms on a pipelined transputer network

The implementation of three parallel sorting algorithms, namely binary sort, odd-even transposition sort and bitonic sort, on a network of transputers is analysed in the paper. The variation in the performance of these algorithms as the number of processors and sort size are changed is investigated. Experimental results show that when up to eight transputers are used, connected as a linear pipeline configuration, all three algorithms can achieve reasonable speedup ratios. The bitonic sort, binary sort odd-even transposition sort achieve speedup ratios of 5, 4.4 and 4, respectively, when eight processors are used to sort 100,000 integers. Analytical models are derived which can be used to predict the performance of the three algorithms when a linear pipeline configuration is used. The predicted performance of the algorithms is compared with the experimental performance in order to validate the model. When the models are used to predict the performance using 16 transputers, it is found that the speedup does not significantly improve compared to the performance achieved with eight transputers. This shows that interprocessor communication has a significant effect on the algorithmic performance when a larger number of processors are used. The conclusions reinforce the fact that the binary and bitonic sorting algorithms are not well-suited to a linear pipeline configuration and that they may perform better if a different topology were used, for example a mesh or a cube connection scheme. Further, the analytical technique used for performance modelling as elaborated in the paper can be employed profitably for other multiprocessor systems as well.

A fast pipelined median filter network

Among image enhancement methods, median filtering is an efficient technique to remove noise. In this note, we present a new median filter network which is cascaded by a half bitonic sorter and two smaller tree networks. Under the same time bound, the number of cells used in our network is less than that of the best-known result.

Massive parallelization of divide-and-conquer algorithms over powerlists

We present transformation rules to parallelize divide-and-conquer (DC) algorithms over powerlists. These rules convert the parallel control structure of DC into a sequential control flow, thereby making the implicit massive data parallelism in a DC scheme explicit. The results given here are illustrated by many examples including Fast Fourier Transform and Batcher's bitonic sort.

FAULT-TOLERANT DESIGN OF BATCHER-BANYAN CLASS ATM SWITCHES

Many proposed packet switching systems for high-speed networks have employed the Batcher–banyan fabric due to its modular structure, self-routeing functionality, and distributed conflict-resolving mechanism. In this paper, we present a systematic fault-tolerant design for the Batcher–banyan class of switches. Our first concern is the development of an on-line error detection mechanism which is the prerequisite of any effective fault tolerant operation. Based on the technique developed by Davis, we propose a general fault-testing technique and verify it for a variety of unique-path self-routeing networks. Furthermore, we extend this method to Batcher sorting networks and construct a fault-tolerant Batcher sorter. Lastly, after contemplating the technique constraints and system performance, we deploy the above techniques into different levels of the Batcher–banyan networks and achieve a fault-tolerant version of the StarBurst switch, a member of the Batcher–banyan class of switches.

The REFINE multiprocessor — theoretical properties and algorithms

A reconfigurable interconnection network based on a multi-ring architecture called REFINE is described. REFINE embeds a single 1-factor of the Boolean hypercube in any given configuration. The mathematical properties of the REFINE topology and the hardware for the reconfiguration switch are described. The REFINE topology is scalable in the sense that the number of interprocessor communication links scales linearly with network size whereas the network diameter scales logarithmically with network size. Primitive parallel operations on the REFINE topology are described and analyzed. These primitive operations could be used as building blocks for more complex parallel algorithms. A large class of algorithms for the Boolean n-cube which includes the FFT and the Batcher's bitonic sort is shown to map efficiently on the REFINE topology. The REFINE multiprocessor is shown to offer a cost-effective alternative to the Boolean n-cube multiprocessor architecture without substantial loss in performance.

Perfect-shuffle interconnected bitonic sorter: optoelectronic design

The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.

Analysis and design of an analog sorting network

An analog sorting neural network is presented. First, existing order representations are discussed and a generalized order representation is introduced. The sorting problem is then formulated as the assignment problem. Based on the assignment problem formulation, the neural network architecture is described. Design principles and an op-amp based circuit realization of the analog neural network are delineated. Three illustrative examples are also discussed to demonstrate the capability and performance of the analog neural network. The proposed analog neural network is shown to be capable of monotonic and bitonic sorting and suitable for hardware implementation.