Bitwise Research Articles

An efficient medical data encryption scheme using selective shuffling and inter-intra pixel diffusion IoT-enabled secure E-healthcare framework

Security in e-healthcare applications such as Telemedicine is crucial in safeguarding patients’ sensitive data during transmission. The proposed system measures the patient’s health parameters, such as body temperature and pulse rate, using LM35 and pulse sensors, respectively. The sensor data and the patient’s medical image are encrypted in the Raspberry Pi 3 B + processor using Python’s proposed text and medical image encryption scheme. The encrypted data is transmitted via the Thing Speak cloud and received by another Raspberry Pi at the receiver to decrypt the cipher data. The flask webserver can view the decrypted data by the doctor at the other end. This IoT implementation of secure Electronic Health Record (EHR) transmission employs text and medical image encryption schemes using a Combined Chaotic System (CCS). The CCS generates the chaotic key sequences to shuffle the medical image row-wise and column-wise. Then, selective shuffling between the cut-off points breaks the statistical relationship between the neighbouring pixels. Finally, the intra and inter-pixel diffusion is carried out using bit permutation and bit-wise XOR operation to create a highly random cipher image. The initial seed for inter-pixel diffusion is obtained from the hash of intra-pixel diffused images to resist chosen plain text and cipher text attacks. The efficiency of the developed medical image encryption algorithm is tested against various attack analyses. The results and the security analyses validate the effectiveness of the proposed scheme.

Lightweight, Post-Quantum Secure Cryptography Based on Ascon: Hardware Implementation in Automotive Applications

With the rapid growth of connected vehicles and the vulnerability of embedded systems against cyber attacks in an era where quantum computers are becoming a reality, post-quantum cryptography (PQC) is a crucial solution. Yet, by nature, automotive sensors are limited in power, processing capability, memory in implementing secure measures. This study presents a pioneering approach to securing automotive systems against post-quantum threats by integrating the Ascon cipher suite—a lightweight cryptographic protocol—into embedded automotive environments. By combining Ascon with the Controller Area Network (CAN) protocol on an Artix-7 Field Programmable Gate Array (FPGA), we achieve low power consumption while ensuring high performance in post-quantum-resistant cryptographic tasks. The Ascon module is designed to optimize computational efficiency through bitwise Boolean operations and logic gates, avoiding resource-intensive look-up tables and achieving superior processing speed. Our hardware design delivers significant speed improvements of 100 times over software implementations and operates effectively within a 100 MHz clock while demonstrating low resource usage. Furthermore, a custom digital signal processing block supports CAN protocol integration, handling message alignment and synchronization to maintain signal integrity under automotive environmental noise. Our work provides a power-efficient, robust cryptographic solution that prepares automotive systems for quantum-era security challenges, emphasizing lightweight cryptography’s readiness for real-world deployment in automotive industries.

Enhancing Blockchain Security by Developing the SHA256 Algorithm

Security plays a vital role in various domains, including blockchain technology. The Blockchain serves as a secure data structure for storing transactional records. Hash functions are employed in cryptography to ensure integrity and authentication within the blockchain. The widely used SHA256 algorithm has faced recent attacks, prompting the development of stronger hash functions. This paper presents a novel modification approach to enhance the performance of SHA256 by introducing an extended mechanism for generating a 288-bit message digest and reducing the number of rounds to 44 instead of 64 while preserving the diffusion of data through its complex iterative process, which involves multiple rounds of bitwise and logical operations. The change makes sure that even small changes to the input data cause noticeable variations in the output hash, thereby maintaining cryptographic properties. The suggested hash function SHA288 achieves improved security, collision resistance, and preimage resistance, while maintaining a faster execution time compared to SHA256. The tables and tests conducted on the suggested algorithm have revealed its remarkable safety and robustness in countering attacks as well as demonstrated outstanding performance in random tests, which further enhances its security measures.

Design and Implementation of Digital Integrated Circuit Based CPU

This paper presents a simplified 16-bit CPU design and its implementation using digital integrated circuits developed with Verilog hardware description language, while emphasizing simulation through the EDA tool. This design puts more emphasis on the critical roles played by the data path and the control unit, executing key instructions including arithmetic operations such as addition, subtraction, bitwise logic, and conditional jumps. This structurally modular CPU is both functioning and stable in nature, allowing support for future enhancements and enhancements as well, thereby serving as an effective model towards an understanding of the principles of CPU design. The execution of these basic instructions puts the core of the CPU under test and reaffirms its proper operation in respect of the detailed instruction set, while its extensibility design confirms further improvement possibilities for future complex instructions as well as finite-state machine optimization for the control unit. The present work not only proves the possibility of creating a fully working CPU, using readily available bare minimum resources to implement a prototype, but is also a breakthrough in future research with CPU architecture. The obtained results will shed light on CPU functionality optimization and extension, being the ground for building more powerful and effective processors in the future.

BWBEV: A Bitwise Query Processing Algorithm for Approximate Prefix Search

We tackle the challenge of conducting an approximate prefix search within datasets of strings. We explore using a bit-parallelism technique to compute the edit distance between distinct strings and illustrate its adaptation for an approximate prefix search procedure referred to as BWBEV. This technique employs a unary representation of edit vectors alongside bitwise operations to efficiently update these vectors during the edit distance computation. We also show how to apply our new bit-parallelism technique strategy to online edit distance computation between strings without index structure. Our experiments with BWBEV applied to approximate prefix search for a query autocompletion task revealed a substantial acceleration of over 36% when contrasted against state-of-the-art methods.

Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory

The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digital computations. The proposed configurable memory unit operates in three modes: (1) memory mode in which it works as a normal dynamic memory, (2) logic–arithmetic mode where it performs bit-wise Boolean logic and full adder operations on two words stored within the memory array, and (3) convolution mode in which it executes digitally XNOR-and-accumulate (XAC) operation for binarized neural networks. A 1.0-V 4096-word × 8-bit computational DRAM implemented in a 45-nanometer CMOS technology performs memory, logic and arithmetic operations at 241, 229, and 224 MHz while consuming the energy of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, it saves energy and latency of the arithmetic operation by at least 47% and 46%, respectively. For VDD = 1.0 V, the proposed CIM unit performs two 128-input XAC operations at 292 MHz with an energy consumption of 20.8 pJ/cycle, achieving 24.6 TOPS/W. This marks at least 11.9× better energy efficiency and 38.8× better delay, thereby achieving at least 461× better energy-delay product than traditional 8-bit wide computing hardware.

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

HybridSA: GPU Acceleration of Multi-pattern Regex Matching using Bit Parallelism

Multi-pattern matching is widely used in modern software for applications requiring high throughput such as protein search, network traffic inspection, virus or spam detection. Graphics Processor Units (GPUs) excel at executing massively parallel workloads. Regular expression (regex) matching is typically performed by simulating the execution of deterministic finite automata (DFAs) or nondeterministic finite automata (NFAs). The natural implementations of these automata simulation algorithms on GPUs are highly inefficient because they give rise to irregular memory access patterns. This paper presents HybridSA, a heterogeneous CPU-GPU parallel engine for multi-pattern matching. HybridSA uses bit parallelism to efficiently simulate NFAs on GPUs, thus reducing the number of memory accesses and increasing the throughput. Our bit-parallel algorithms extend the classical shift-and algorithm for string matching to a large class of regular expressions and reduce automata simulation to a small number of bitwise operations. We have developed a compiler to translate regular expressions into bit masks, perform optimizations, and choose the best algorithms to run on the GPU. The majority of the regular expressions are accelerated on the GPU, while the patterns that exhibit random memory accesses are executed on the CPU in parallel. We evaluate HybridSA against state-of-the-art CPU and GPU engines, as well as a hybrid combination of the two. HybridSA achieves between 4 and 60 times higher throughput than the state-of-the-art CPU engine and between 4 and 233 times better than the state-of-the-art GPU engine across a collection of real-world benchmarks.

Optimizing Data Flow in Binary Neural Networks.

Binary neural networks (BNNs) can substantially accelerate a neural network's inference time by substituting its costly floating-point arithmetic with bit-wise operations. Nevertheless, state-of-the-art approaches reduce the efficiency of the data flow in the BNN layers by introducing intermediate conversions from 1 to 16/32 bits. We propose a novel training scheme, denoted as BNN-Clip, that can increase the parallelism and data flow of the BNN pipeline; specifically, we introduce a clipping block that reduces the data width from 32 bits to 8. Furthermore, we decrease the internal accumulator size of a binary layer, usually kept using 32 bits to prevent data overflow, with no accuracy loss. Moreover, we propose an optimization of the batch normalization layer that reduces latency and simplifies deployment. Finally, we present an optimized implementation of the binary direct convolution for ARM NEON instruction sets. Our experiments show a consistent inference latency speed-up (up to 1.3 and 2.4× compared to two state-of-the-art BNN frameworks) while reaching an accuracy comparable with state-of-the-art approaches on datasets like CIFAR-10, SVHN, and ImageNet.

HTQ: Exploring the High-Dimensional Trade-Off of mixed-precision quantization

Mixed-precision quantization, where more sensitive layers are kept at higher precision, can achieve the trade-off between accuracy and complexity of neural networks. However, the search space for mixed-precision grows exponentially with the number of layers, making the brute force approach infeasible on deep networks. To reduce this exponential search space, recent efforts use Pareto frontier or integer linear programming to select the bit-precision of each layer. Unfortunately, we find that these prior works rely on a single constraint. In practice, model complexity includes space complexity and time complexity, and the two are weakly correlated, thus using simply one as a constraint leads to sub-optimal results. Besides this, they require manually set constraints, making them only pseudo-automatic. To address the above issues, we propose High-dimensional Trade-off Quantization (HTQ), which automatically determines the bit-precision in the high-dimensional space of model accuracy, space complexity, and time complexity without any manual intervention. Specifically, we use the saliency criterion based on connection sensitivity to indicate the accuracy perturbation after quantization, which performs similarly to Hessian information but can be calculated quickly (more than 1000× speedup). The bit-precision is then automatically selected according to the three-dimensional (3D) Pareto frontier of the total perturbation, model size, and bit operations (BOPs) without manual constraints. Moreover, HTQ allows for the joint optimization of weights and activations, and thus the bit-precisions of both can be computed concurrently. Compared to state-of-the-art methods, HTQ achieves higher accuracy and lower space/time complexity on various model architectures for image classification and object detection tasks. Code is available at: https://github.com/zkkli/HTQ.

A succinct and approximate greedy algorithm for the Minimum Set Cover Problem

The Minimum Set Cover Problem (MSCP) is a combinatorial optimization problem belonging to the NP-Hard class in computer science. For this reason, there is no algorithm that in the worst case ensures finding an optimal solution in polynomial-time. For a given universe X, the popular greedy heuristic, called Greedy-SetCover, is the main theoretical contribution to obtain an approximate solution for the MSCP in polynomial-time, offering an optimal approximate ratio of (ln|X|+1). In this article, we propose an approximate algorithm for MSCP within a succinct representation of the input dataset, whose empirical performance improves Greedy-SetCover both in quality and execution time, while offering the same optimal approximation ratio for the problem. Our experiments show that the proposed algorithm is magnitudes of times faster than the aforementioned greedy one, obtaining on average a cardinality much closer to the optimal solution. Furthermore, because we work on a succinct representation that allows us to compute operations between sets using bitwise operators, we can process much larger datasets than state-of-the-art solutions. As a result, our proposal is also a suitable alternative for processing large datasets as required by the current Big Data era.

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset

This research paper introduces a memory architecture that handles standard memory storage operations and enables in-memory computations, surpassing the capabilities of conventional SRAM bit-cells. The proposed architecture in this work effectively eliminates read-disturb issues and facilitates bit-wise operations like NAND, NOR, and XNOR, all without requiring intricate analog peripheral circuits. The suggested bit-cell architecture offers enhanced throughput compared to existing In-Memory Computing (IMC) bit-cell architectures, making it a more suitable design for IMC applications. Parallelism offers enhanced throughput due to the unique bit-cell architecture, which allows all the bit-wise operations to be achieved simultaneously in a single cycle. The validity of the suggested architecture has been confirmed through Monte-Carlo variation analysis, utilizing UMC 28 nm PDK transistor models to ensure its robustness. Furthermore, architecture is benchmarked using the CIFAR-10 dataset, which entails assessing its performance across various machine learning models via the NeuroSim Simulator. The proposed architecture offers a substantial increase of up to 40 % in throughput (TOPS/W) compared to the existing architectures. Utilizing accurate Monte-Carlo simulations with 1000 samples, the stability of the proposed 10T bit-cell is validated at worst-case PVT corners, up to 6σ variations.

OEM: An operation-aware event matching algorithm for content-based Pub/Sub systems

Due to the continuous expansion of the user base and the heightened demands for quality of service (QoS), real-time data distribution has encountered significant challenges in event matching within large-scale content-based publish/subscribe (CPS) systems. Many efficient algorithms have been proposed to enhance the matching performance. However, most existing algorithms scarcely consider operation characteristics, which often leads to performance degradation due to a multitude of repetitive operations, such as comparisons, additions, and assignments. In this paper, we propose an Operation-aware Event Matching algorithm called OEM, which takes into account the efficiency of CPU operations, SIMD instructions, and multi-thread architecture. First, we introduce a bitset-based subscription cache mechanism (SCM), which enables the efficient execution of bitwise OR operations during the matching process. Furthermore, we propose two optimizations, namely an optimal skewness-aware cell grouping (OSCG) strategy and an attribute-based clustering mechanism (ACM), to enhance the efficiency of OEM. These optimizations effectively address the challenges posed by data skewness, low cache efficiency, and high dimensionality. In addition, we establish a performance analysis model that characterizes the trade-off between memory consumption and performance improvement. We conducted extensive experiments to evaluate the performance of OEM. Compared to six state-of-the-art algorithms, namely REIN, Ada-REIN, TAMA, OpIndex, PEM and fgPEM, OEM achieves an average reduction in matching time by 40.4×, 38.5×, 12.0×, 33.1×, 27.8×, and 25.5×, respectively.

Long distance all-optical logic operations through a single multimode fiber empowered by wavefront shaping

Multimode fibers (MMFs) are a promising solution for high-throughput signal transmission in the time domain. However, crosstalk among different optical modes within the MMF scrambles input information and creates seemingly random speckle patterns at the output. To characterize this process, a transmission matrix (TM) can be used to relate input and output fields. Recent innovations use TMs to manipulate the output field by shaping the input wavefront for exciting advances in deep-brain imaging, neuron stimulation, quantum networks, and analog operators. However, these approaches consider input/output segments as independent, limiting their use for separate signal processing, such as logic operations. Our proposed method, which makes input/output segments as interdependent, adjusts the phase of corresponding output fields using phase bias maps superimposed on input segments. Coherent superposition enables signal logic operations through a 15-m-long MMF. In experiments, a single optical logic gate containing three basic logic functions and cascading multiple logic gates to handle binary operands is demonstrated. Bitwise operations are performed for multi-bit logic operations, and multiple optical logic gates are reconstructed simultaneously in a single logic gate with polarization multiplexing. The proposed method may open new avenues for long-range logic signal processing and transmission via MMFs.

SPIMulator: A Spintronic Processing-In-Memory Simulator for Racetracks

In-memory processing is becoming a popular method to alleviate the memory bottleneck of the von Neumann computing model. With the goal of improving both latency and energy cost associated with such in-memory processing, emerging non-volatile memory technologies, such as Spintronic magnetic memory, are of particular interest as they can provide a near-SRAM read/write performance and eliminate nearly all static energy without experiencing any endurance limitations. Spintronic Racetrack Memory (RM) further addresses density concerns of spin-transfer torque memory (STT-MRAM). Moreover, it has recently been demonstrated that portions of RM nanowires can function as a polymorphic gate, which can be leveraged to implement multi-operand bulk bitwise operations. With more complex control, they can also be leveraged to build arithmetic integer and floating point processing in memory (PIM) primitives. This paper proposes SPIMulator, a Spintronic PIM sim ulator that can simulate the storage and PIM architecture of executing PIM commands in Racetrack memory. SPIMulator functionally models the polymorphic gate properties recently proposed for Racetrack memory, which allows transverse access that determines the number of ‘1’s in a segment of each Racetrack nanowire. From this simulation, SPIMulator can report real-time performance statistics such as cycle count and energy. Thus, SPIMulator simulates the multi-operand bit-wise logic operations recently proposed and can be easily extended to implement new PIM operations as they are developed. Due to the functional nature of SPIMulator, it can serve as a programming environment that allows development of PIM-based codes for verification of new acceleration algorithms. We demonstrate the value of SPIMulator through the modeling and estimations of performance and energy consumption of a variety of example applications, including the Advanced Encryption Standard (AES) for encryption primarily based on logical and look-up operations; multiplication of matrices, a frequent requirement in scientific, signal processing, and machine learning algorithms; and bitmap indices a common search table employed for database lookups.

An efficient and lightweight image encryption technique using Lorenz chaotic system

In the past few years, to store and transmit image data securely, numerous research initiatives on image encoding have been conducted. The primary objective of the image encryption technique is to safeguard the image by sabotaging the pixel pattern. Researchers suggested a safe, portable, and simple to use image encryption technique in this work. The encryption of the image is done using a bit-wise XOR operation, where the bit-wise operation is applied on each pixel of the plain image with a pseudo-random number that is created by the Lorenz chaotic system, to prevent unwanted access to confidential image data. The results of the experiments demonstrate that the suggested technique offers effective image encryption and decryption. The key stream of the encrypted image is made up of pseudo-random digits generated by the Lorenz Chaotic System. Several experimental tests have been performed, including histogram, correlation, information entropy, and differential analysis. The experimental findings reveal that the suggested approach performs image encryption and decryption efficiently.

Securing air defense visual information with hyperchaotic Folded Towel Map-Based encryption

<p>In modern air defense systems, safeguarding sensitive information is crucial to prevent unauthorized access and cyber-attacks. Here, we present an innovative image encryption approach, leveraging chaotic logistic maps and hyperchaotic Folded Towel Map sequence generation. The proposed image encryption is a multi-layered procedure intended to secure image transmission. It initiates with permutation, where a chaotic logistic map generates pseudo-random sequences to scramble pixel positions. Next, key mixing creates complexity, randomness, and nonlinearity using an invertible key matrix. Finally, the diffusion phase employs hyperchaotic maps to produce a new sequence XORed with the pixels through a bitwise operation, further encrypting the image. This three-stage process efficiently protects images from unauthorized access, ensuring secure transmission. The proposed method enhances security by leveraging non-linearity, sensitivity, and robust mixing, properties making it highly resistant to cryptographic attacks. The experimental results showed robust encryption performance as established by metrics such as an entropy value of 7.9991, a UACI of 33.21%, and an NPCR of 99.61%. The proposed encryption approach outperformed existing methods in securing image transmission and storage, offering a reliable solution for protecting air defense communication strategic data.</p>

Fully Connected Networks on a Diet With the Mediterranean Matrix Multiplication.

This article proposes the Mediterranean matrix multiplication, a new, simple and practical randomized algorithm that samples angles between the rows and columns of two matrices with sizes m, n, and p to approximate matrix multiplication in O(k(mn+np+mp)) steps, where k is a constant only related to the precision desired. The number of instructions carried out is mainly bounded by bitwise operators, amenable to a simplified processing architecture and compressed matrix weights. Results show that the method is superior in size and number of operations to the standard approximation with signed matrices. Equally important, this article demonstrates a first application to machine learning inference by showing that weights of fully connected layers can be compressed between 30 × and 100 × with little to no loss in inference accuracy. The requirements for pure floating-point operations are also down as our algorithm relies mainly on simpler bitwise operators.

Toward Accurate Binarized Neural Networks With Sparsity for Mobile Application.

While binarized neural networks (BNNs) have attracted great interest, popular approaches proposed so far mainly exploit the symmetric sign function for feature binarization, i.e., to binarize activations into -1 and +1 with a fixed threshold of 0. However, whether this option is optimal has been largely overlooked. In this work, we propose the Sparsity-inducing BNN (Si-BNN) to quantize the activations to be either 0 or +1, which better approximates ReLU using 1-bit. We further introduce trainable thresholds into the backward function of binarization to guide the gradient propagation. Our method dramatically outperforms the current state-of-the-art, lowering the performance gap between full-precision networks and BNNs on mainstream architectures, achieving the new state-of-the-art on binarized AlexNet (Top-1 50.5%), ResNet-18 (Top-1 62.2%), and ResNet-50 (Top-1 68.3%). At inference time, Si-BNN still enjoys the high efficiency of bit-wise operations. In our implementation, the running time of binary AlexNet on the CPU can be competitive with the popular GPU-based deep learning framework.

Hypercube Stereoisograms as Efficient Graphs to Represent the Stereoisomeric Relationships of Organic Molecules Containing 1 to 4 Stereogenic Centers

The n-dimensional unit hypercubes, Qn (n = 1 to 4), are used as n-dimensional graphs (Stereoisograms) to describe the stereoisomeric (enantiomeric and/or diastereomeric) relationships of molecules containing one to four RS-stereogenic centers. To achieve this goal, the strings of 0’s and 1’s, used for labelling the vertices of unit hypercubes, are substituted by strings of R’s and S’s-descriptors coming from the CIP priority rules. The development of those ndimensional unit hypercubes along ordered axes and the application of combinatorial techniques allow to locate the enantiomeric pairs at antipodal vertices (points related by a chirality center, which satisfies the bitwise operation known as “NOT”); whereas diastereomers are related by mirror planes, whose reflection results in a partial permutation of the RS-descriptors. These facts are in good agreement with the literature and the principles of the combinatorial theory applied to such hypercubes. On the other hand, because the maximum number of stereoisomers 2n is not always held, “pseudo hypercubes” containing one or more “ghost vertices” are proposed to include the meso (achiral) stereoisomers