Bit-stream Signal Research Articles

High-Linearity High-Resolution Time-of-Flight Linear-Array Digital Image Sensor Using Time-Domain Feedback.

This paper presents a high-linearity high-resolution time-of-flight (ToF) linear-array digital image sensor using a time-domain negative feedback technique. A coarse ToF measurement loop uses a 5-bit digital-to-time converter (DTC) and a delayed gating-pulse generator for time-domain feedback to find the zero of the difference between ToF and the digital estimate of the gating-pulse delay while maintaining a constant operating point of the analog readout circuits. A fine ToF measurement uses a delta-sigma modulation (DSM) loop using the time-domain feedback with a bit-stream signal form. Because of the self-contained property of the DSM for low distortion and noise exploited by the oversampling signal processing, the proposed technique provides high-linearity and high-range resolution in the fine ToF measurement. A prototype ToF sensor of 16.8 × 16.8 μm2 two-tap pixels and fabricated in a 0.11 μm (1P4M) CMOS image sensors (CIS) process achieves +0.9%/−0.47% maximum nonlinearity error and a resolution of 0.24 mm (median) for the measurement range of 0–1.05 m. The ToF sensor produces an 11-bit fully digital output with a ToF measurement time of 22.4 ms.

Bitstream radar waveforms for generic single-chip radar

Bitstreams, square wave digital signals, enable flexible radar implementations in modern digital technology. By using bitstreams in place of analog sinusoidal waveforms, we can realize continuous-wave (CW), stepped-frequency CW, frequency-modulated CW, or even pseudo random noise-sequence and pulsed radars, all with a single bit of amplitude resolution. The building blocks are a programable waveform generator, a sweep threshold quantizer, digital delay, and a digital XOR gate as a mixer. This gives us a novel, almost fully digital (requiring only a comparator) system, as previously proposed and which is extended here. The flexibility of the transmitter allows for easy switching between waveforms and the bitstream signal can be processed with single-bit digital gates. Single-bit signals allows for exploration of novel continuous time non-clocked digital implementations to maximize speed and energy efficiency. Mixing frequencies with a digital XOR gate creates harmonics, which are explored for multiple solutions utilizing digital delay. Analytical as well as simulation results are presented. Initial measurements from a 90 nm CMOS chip is provided for the transmitter and the full system, proving the feasibility of a digital future in radar.

A 4 GHz CMOS multiplier for sigma—delta modulated signals

An integrated circuit design of a high speed multiplier for direct sigma—delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.

Techniques for Conditioning Bit-Stream Signals for Single-Phase Power Electronics Applications

Bitstream-based control, which uses one-bit-wide signals to control power electronics applications, is a new approach for controller design. Bit-Stream signals can be directly applied to control electronic devices, but the high-frequency nature of bitstream signals can lead to excessive switching losses. Thus, it is essential to downsample bitstream signals to reduce switching losses to acceptable levels. This paper presents a novel modulator, which downsamples high-frequency bitstreams to low-frequency switching signals that are suitable for driving two-level half-bridge or three-level full-bridge inverters. Methods for compensating for switch dead time and balancing switching losses of the inverter legs are presented, and the performance of the proposed modulators are compared to the standard pulse width modulation strategies. Simulation and experimental results of a 2-kW single-phase inverter show that the proposed bitstream modulators consume fewer logic resources, produce spread-spectrum output currents, and can deliver lower total harmonic distortion than similar fixed-frequency pulse width modulators.

Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables.

Bit-Stream Adders and Multipliers for Tri-Level Sigma–Delta Modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.

Bit-stream signal processing and its application to communication systems

The paper describes a digital circuit technique to process directly bit-stream signals from sigma–delta modulation based analogue-to-digital converters and the application of the technique to communication systems. The newly developed adder and multiplier are fundamental processing circuit modules. Using the fundamental modules and up/down counters, other circuit modules, such as oscillators, dividers and square root circuits, can also be realised. Signal processors built from the modules have three advantages over multi-bit Nyquist rate processors. First, single-bit/multibit converters are not needed at the inputs of the processors because the arithmetic modules directly process the bit-stream signals. Secondly, the physical areas for routing the signals among the circuit modules are small since they are in the form of a bit-stream. Thirdly, the processors are built from a smaller number of logic gates than conventional Nyquist rate processors because of the simple structure of the circuit modules. As an application of the technique to digital signal processing for communications, a QPSK demodulator is presented. In addition to circuit simulations of the demodulator, a useful linear analysis to estimate the influence of the noise components contained in the outputs from the circuit modules on the steady-state demodulation performance is explained.