Bit-slice Research Articles

A microprogrammable peripheral unit and the FFT

A circuit based on the AM2901 bit slice processor and a serial/parallel multiplier is described along with the algorithm to compute the base-2 DIF fast Fourier transform.

Test generation by activation and defect-drive (TEGAD)

This paper describes an efficient test generation method based on activation and defect-drive using random patterns. The activation process generates patterns to control any circuit node to 0 and 1. After the activation process, the defect-drive propagates the faulted signal, step by step, towards the external output by using parallel fault simulation. The applications are discussed for several gate arrays and micro-processors. The computer run time for the test generation was observed to be proportional to the number of nodes to the power of 1.7 in the case of bit-slice microprocessors. The improvement in manual patterns by the addition of the generated ones was also demonstrated.

A 4800 bit/s microprocessor-based CCITT compatible data modem

The microprocessor-based implementation of data modems has been attracting a great deal of scientific interest in the past decade. It is a kind of interdisciplinary field where both information theory and microprocessor engineering strongly interact. A number of different microprocessor-based modems are available on the market. Most of the modems with speeds above 2400 bit/s are commonly implemented on bit-slice processors (e.g., AMD 2900) or fast and expensive MOS microprocessors (e.g., TMS 320). For these speeds, it is considered that slow and cheap MOS microprocessors (e.g., Intel 8085) can be used only at the cost of simplifications in the algorithms for signal demodulation and detection, i.e., at the cost of decreased performance. This paper, however, describes a MOS microprocessor-based implementation of the 4800 bit/s modem which was achieved without any deterioration of the modem performance. Both algorithmic details (connected with the processing of signals) and implementational details (connected with the microprocessor-based implementation) are given.

Microprocessor Aided Data Acquisition at VEDAS

Three microprocessor systems have been developed to support data acquisition in nuclear physics multiparameter experiments. A bit-slice processor accumulates up to 256 1-dim spectra and 16 2-dim spectra. A microprocessor, based on the AM 29116 ALU, performes a fast consistency check on the coincidence data. A VME-Bus double-processor displays a colored scatterplot.

Binary Passband Echo Canceller in a 4800 Bit/s Two-Wire Duplex Modem

This paper deals with the echo cancellation applied to highspeed (4800 bit//s or higher) voiceband data modems. Simple echo cancellers are presented for the whole range of data bit rates from 1200 bit//s to 9600 blt/s. Their structure full=y integrates the modulation process and especially exploits the various relationships existing between the modulation rate and the carrier frequency. The generation of the echo replica is performed by duplicating components of the line echo from simple coded binary symbols processed at the modulation rate only. The implementation of these binary passband echo cancellers can be made quite simple by properly selecting the coded binary symbols from the user's data. The application of these principles to a 4800 bit/s two-wire duplex modem is then highlighted. The essential characteristics of the modem echo canceller are outlined and its implementation with bit slice processors is described. Finally, test results on the switched telephone network and on satellite links are presented.

Signal Detection Using Bit-Slice Microprocessors

A bit-slice microprocessor configuration is presented which is applicable to implementation of real-time signal detection algorithms. The general hardware configuration and appropriate software functions are described. General algorithms which are of wide utility in signal detection applications are discussed in the context of the defined hardware configuration. To facilitate the presentation and indicate the practicality of this system configuration, the application of the hardware configuration and software techniques to target detection for passively received signals using multiple receive beams is discussed.

Microcomputer Control of Power Converters

Thyristor power converters are charac terized by an inherent discrete control action and are, therefore, particularly well suited to on-line control by microcomputers. The paper presents a new design of digital controllers based upon powerfull 16-bit or bit-slice microprocessors, which provide high firing time resolution and enough computing power to implement sophis ticated control strategies. Both hardware and software are discussed, with special emphasis on the firing con trol algorithms. The properties of Pulse Frequency Con trol (PFC) and Pulse Phase Control (PPC) are examined and small-signal discrete models are presented. These models are used in the analysis of constant current and constant extinction angle control through the z-transform method.

Using APL to understand bit-slice microprocessors

This paper describes strategies used for the rapid construction of a microprogram assembler and simulator written in APL. Although the motivation for the work was learning and teaching, and although both designs are simple and superficially ad-hoc, the approach is easily applicable in a routine way to other systems and requires little more effort than that involved in writing the definition files for general purpose simulators and assemblers, the work of the latter being mainly done by the APL interpreter.

A hardware stochastic interpolator for raster displays

Stochastic modeling has found uses so far mainly for expensive very realistic graphics display. The cost of rendering is not intrinsic to the technique, but mainly due to the high resolution and the sophisticated display techniques which accompany it. We describe here a basic tool for a less expensive approach to stochastic modeling which is designed for a more “down to earth” type of application, and brings the display of stochastic models nearer to real-time. A special purpose board for stochastic interpolation has been built, which can generate an array of up to 129×129 12 bit stochastic values to be used by the rest of the display system as a texture source, or for more elaborate algorithms. The board functions as a coprocessor in a traditional frame buffer system, and includes a micro-coded bit-slice processor, a multiplier, special hardware to generate uniformly distributed random numbers, memory to store a look-up table for random numbers with the required distribution, and two buffers for the resulting arrays. The current implementation generates values at less than 4 microseconds per point, and in conjunction with a standard graphics processor can display nearly 10000 stochastic points in real-time, or can update a full screen of stochastic values in less than one second. Illustrations are given of the output of the board and of pictures and animations generated with it.

Fault diagnosis of bit-slice processor

This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. Fault detection and fault location procedures using the generated test sequence are also presented. Using these procedures, a test microprogram and diagnostic system for the bit-sliced processor constructed by the array of four Am 2901 bit-slices are developed.

Implementation of a Multirate Speech Digitizer

In this paper, implementation of a compact and efficient multirate speech digitizer with variable transmission rates of 2.4, 4.8, 9.6, and 14.96 kbits/s is presented. The multirate algorithm has been made based on the residual-excited linear prediction (RELP) vocoder with a transmission rate of 9.6 kbits/s. The residual encoder employed in the RELP vocoder uses hybrid companding delta modulation (HCDM). This HCDM is also used as a 14.96 kbit/s coder. If the residual in the RELP system is down-sampled before encoding, a 4.8 kbit/s coder can be realized. If the residual encoder is not used, a 2.4 kbit/s linear predictive coder (LPC) can be realized by incorporating a pitch extractor. In the 4.8 and 9.6 kbit/s coders the pitch-implanted residual excitation method has been used to generate the excitation signal to the synthesis filter. The multirate speech digitizer algorithm has been implemented using 2900 series bit-slice microprocessors. The external memory is composed of 2K RAM's and 2K ROM's. The system design is a two-bus structure with a 204 ns cycle time. With efficient hardware and software design, the multirate speech digitizer requires almost the same hardware complexity as compared with the conventional 2.4 kblt/s LPC vocoder.

Introduction: Computer Arithmetic

SINCE the inception of electronic computers, much effort has been directed towards the search of faster arithmetic techniques. For all scientific computations, the arithmetic units have always been considered as the heart of a digital computer. In the earlier approaches, emphasis on the arithmetic elements was limited to integer arithmetic with limited precision, as the cost of discrete components was the main driving factor. Circuit optimization with reduced components and techniques for high-speed arithmetic were crucial at that time. Later, software techniques were employed to include floating-point representation and to achieve desirable precision. The advances in LSI technology and the inception of microcomputers caused a-great deal of impact on the ways people used to think. Emphasis on circuit component reduction was shifted to iterative logic and minimization of chip types. This led to various uniformly structured and specialized units like cellular arrays, etc. Now, several high-speed multipliers and FFT processors are commercially available. The on-line processing requirement also enhanced acceptance of techniques like overlapping and pipelining. The error analysis has always been a lively topic of interest and so also the variable word-lengths. Parallel processing requirements led to the introduction of bit-slice ALU's. The current trend is to use high-speed arithmetic for various transforms and signal processing applications. This was clearly reflected from the papers submitted for the special issue.

Some Signal Processing Aspects of Time-of-Flight Positron Emission Tomography (TOFPET) System Implementation

The implementation of data acquisition and real-time backprojection via a bit-slice microprocessor system places serious constraints on data format in TOF-PET systems. To minimize hardware costs and complexity and enhance processing speed, internal data representation is to be realized with a minimum number of bits without significant loss of accuracy. Specifically, we have examined in detail data formats necessary for the quantization of the TOF data and reconstruction filtering via integer FFT's. Estimates of data degradation as related to number of bits utilized have been obtained. It is shown that a significant reduction in image memory size and improvement in speed of computation can be achieved with the appropriate choice of data formats and algorithms.

Fast dedicated microprocessor for real-time frequency analysis of ultrasonic blood-velocity measurements

A signal processor has been designed using bit-slice microprocessor techniques. The processor has two data bases for input/output, a central processing unit and a memory. The microprogram in the processor can be changed to suit individual needs. The analysis which is performed at present is a fast Fourier transform (FFT) of ultrasonic blood-velocity signals with graphic display of the results. The FFT operates on 256 sampled points, thus giving 128 frequency components of the signal. Each transform is calculated in less than 4·5 ms. The algorithm of the FFT uses base 2, and the real-valued signal is transformed into a complex sequence to simplify the program. The microprocessor has been interfaced to an ultrasound doppler blood-velocity meter. Results from measurements on arteries are shown.

Review of "Bit-Slice Design: Controllers and ALUs by Donnamarie E. White", Garland STPM Press, 1981

Review of "Bit-Slice Design: Controllers and ALUs by Donnamarie E. White", Garland STPM Press, 1981

Review of "Bit-Slice Microprocessor Design by John Mick and James Brick", McGraw-Hill Book Company, 1980

No abstract available.

High speed front-end processing in the CAMAC interfacing system

In this paper, recent work in the design and application of bit-sliced microprocessor elements to front-end processing in data acquisition and control systems is discussed. A microprogrammed computing structure, based on commercially available Schottky TTL microprocessor slices, performs high speed subroutines at a basic operation time of 142 ns per microcycle. The structure operates in parallel with, and under the control of, a conventional microcomputer system, which is generally interfaced to a more complete system-minicomputer that actually performs the data acquisition or control task.

Meta: A language system for bitslice applications

AbstractBitslice technology is a widely used method for building microprogrammable bitslice processors. Manufacturer supplied language tools required for the production of the microcode, however, are usually too expensive. The Meta system, described in this paper, provides the necessary language facilities at minimal cost, making it ideal for small bitslice projects.The concept of the Meta system is very simple: a description of the datapath structure and the information processing capabilities of the bitslice processor is written using the four basic operations of the Meta language. Meta uses this description to generate a translator for machine‐oriented microprogramming language. This offers the programmer a tool for implementing microprogrammed functions.Because of the simplicity of the Meta system, language translators can be built in a very short period of time.

Teaching bit-slice microprocessor applications using simulation techniques

A case is often made for a greater emphasis on microprogramming techniques at an undergraduate level, particularly in view of the ephemeral nature of fixed instruction set microprocessors. However, the basic principles involved in the design of modern computing machines may be more clearly understood when considered in terms of bit-slice microprocessors. The success of this teaching approach is heavily dependent on the nature of the teaching aids available to the student for the execution of microprogramming exercises. A minicomputer-based interactive digital system simulator is described with a suite of routines for the modelling of a comprehensive range of bit and word processing logic elements and includes models of devices from a widely available bit-slice component family.

A Functional Approach to Testing Bit-Sliced Microprocessors

Bit-sliced microprocessors are representative of an important class of LSI components that can be interconnected in a regular way to construct many useful types of digital systems. This paper develops an analytic test generation methodology for bit-sliced systems. A formal model C for a 1-bit bit-sliced microprocessor is defined which has the main features of many commercially available microprocessors. Using a functional fault model instead of the usual stuck-line fault model, a technique is presented for deriving a complete and near-minimal sequence of tests for C. The basic cell C is extended to form two more general cells Ck and Ck. n. Ck is a k-bit version of C, while Ck, n is Ck with an n × k-bit scratchpad RAM. The internal structure of C4,16 closely resembles that of the AMD 2901 processor slice. Test sequences for these cells are derived in much the same way as for C. It is shown that the test sequence for a single cell (C, Ck, or Ck, n) can easily be extended to a test sequence for an array of N identical cells with no increase in the number of tests required. It is observed that for test generation purposes, bit-sliced microprocessors can be viewed as C-testable iterative logic arrays, which require a constant number of test patterns independent of array size. Some new results on test generation for C-testable systems are presented, as well as a method for modifying iterative logic arrays to make them C-testable.