Bit-parallel Systolic Multipliers Research Articles

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.

Efficient Bit-Parallel Systolic Polynomial Basis Multiplier over GF(28) based on Irreducible Polynomials

Objectives: Multiplication in Galois fields is used in many applications, especially in cryptography. Several algorithms and architectures are proposed in the literature to obtain efficient multiplication operations in Galois fields. Methods/ Statistical Analysis: In this paper, based on a modified interleaved modular multiplication algorithm, a bit-parallel systolic multiplier based on generic irreducible polynomials over Galois Field (GF (28)) is proposed. Theoretical hardware and speed complexity analysis is performed and the proposed multiplier is compared with other systolic multipliers available in the literature for irreducible polynomials. Findings: The proposed systolic multiplier achieves 21.23% reduction in hardware complexity when compared with the best multiplier among existing multipliers for m = 8. Applications/Improvements: The Field-Programmable Gate Array (FPGA) implementation results for the Advanced Encryption Standard (AES) and Two fish algorithms, incorporating the proposed multiplier and some existing designs, are also presented which indicates that the proposed multiplier achieves low area and low power consumption when compared with other systolic multipliers available in the literature.

기약 AOP를 이용한 GF(2m)상의 낮은 지연시간의 시스톨릭 곱셈기

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for <TEX>$GF(2^m)$</TEX> fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2m) Using Toeplitz Matrix-Vector Representation

In this paper, a generalized Montgomery multiplication algorithm in GF(2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pentanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection. Accordingly, they are well suited to VLSI implementation.

New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

A new bit-parallel systolic multiplier over GF(2m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m 2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

Multiplexer-based bit-parallel systolic multipliers over GF(2 m)

Two novel systolic architectures are presented in this paper for polynomial basis finite field multipliers. Using cut-set systolization technique and modified Booth’s recording, we have derived here an efficient realization of multiplexer-based bit-parallel systolic multipliers over GF(2 m ). Our multipliers save about 19% space complexity as compared to traditional multipliers, and involve nearly half of the time-complexity of the corresponding existing design. It is shown that the proposed systolic architectures have significantly lower time–area product than existing systolic multipliers. For cryptographic applications, our proposed architectures can have better the time and space complexity. Moreover, these new multipliers are highly regular, modular, and therefore, well-suited for VLSI implementation.

Low-complexity bit-parallel systolic multipliers over GF(2 m)

This paper presents new time-dependent and time-independent multiplication algorithms over finite fields GF(2 m ) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithm allows efficient realization of the bit-parallel systolic multipliers. The results show that the proposed time-independent multiplier saves about 54% space complexity as compared to other related multipliers for polynomial and dual bases of GF(2 m ). The proposed architectures include the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation.

Scalable and systolic Montgomery multiplier over GF(2m) generated by trinomials

A Montgomery&apos;s algorithm in GF(2m) based on the Hankel matrix–vector representation is proposed. The hardware architecture obtained from this algorithm indicates low-complexity bit-parallel systolic multipliers with irreducible trinomials. The results reveal that the proposed multiplier saves approximately 36% of space complexity as compared to an existing systolic Montgomery multiplier for trinomials. A scalable and systolic Montgomery multiplier is also developed by applying the block-Hankel matrix–vector representation. The proposed scalable systolic architecture is demonstrated to have significantly less time–area product complexity than existing digit-serial systolic architectures. Furthermore, the proposed architectures have regularity, modularity and local interconnectability, making them highly appropriate for VLSI implementation.

Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)

The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2m) according to the Fenn's multiplier in [7]. Although, the proposed method increases the space complexity overhead about 27% and the latency overhead about one extra clock cycle as compared to Fenn's multiplier. Our analysis shows that all single stuck-at faults can be detected concurrently.

Ringed bit-parallel systolic multipliers over a class of fields GF(2 m)

This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2 m ), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.

Low complexity bit-parallel systolic architecture for computing C+ AB2 over a class of GF(2 m)

This work presents a ringed bit-parallel systolic architecture for computing C+ AB 2 over a class of GF(2 m ) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2 m ). The ringed bit-parallel systolic multiplier over the class of GF(2 m ) is free of global connections and requires fewer gates and input pins than the other relative multipliers proposed in Liu et al. (IEICE Trans. Fundam. E83-A (12) (2000) 2657) and Lee et al. (IEEE Trans. Circuits Syst. II 48(5) (2001) 519; 15th IEEE Symposium on Computer Arithmetic (Arith-2001), Vail, CO, USA, June 2001, p. 51). Moreover, this ringed configuration can be easily implemented in VLSI systems by taking the advantage of three-dimensional routing.

Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials

A bit-parallel systolic multiplier in the finite field GF(2m) over the polynomial basis, where irreducible trinomials xm+xn+1 generate the fields GF(2m) is presented. The latency of the proposed multiplier requires only 2m−1 clock cycles. The architecture has the advantage of low latency, low circuit complexity and high throughput, as compared with traditional systolic multipliers. Moreover, the multiplier is highly regular, modular, and therefore, well-suited for VLSI implementation.

Bit-parallel systolic multipliers for GF(2/sup m/) fields defined by all-one and equally spaced polynomials

Two operations, the cyclic shifting and the inner product, are defined by the properties of irreducible all one polynomials. An effective algorithm is proposed for computing multiplications over a class of fields GF(2/sup m/) using the two operations. Then, two low-complexity bit-parallel systolic multipliers are presented based on the algorithm. The first multiplier is composed of (m+1)/sup 2/ identical cells, each consisting of one 2-input AND gate, one 2-input XOR gate, and three 1-bit latches. The other multiplier comprises of (m+1)/sup 2/ identical cells and mXOR gates. Each cell consists of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. Each multiplier exhibits very low latency and propagation delay and is thus very fast. Moreover, the architectures of the two multipliers can be applied in computing multiplications over the class of fields GF(2/sup m/) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m.

Low-latency bit-parallel systolic multiplier

A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.