Low complexity bit-parallel systolic architecture for computing C+ AB2 over a class of GF(2 m)

Abstract

This work presents a ringed bit-parallel systolic architecture for computing C+ AB 2 over a class of GF(2 m ) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2 m ). The ringed bit-parallel systolic multiplier over the class of GF(2 m ) is free of global connections and requires fewer gates and input pins than the other relative multipliers proposed in Liu et al. (IEICE Trans. Fundam. E83-A (12) (2000) 2657) and Lee et al. (IEEE Trans. Circuits Syst. II 48(5) (2001) 519; 15th IEEE Symposium on Computer Arithmetic (Arith-2001), Vail, CO, USA, June 2001, p. 51). Moreover, this ringed configuration can be easily implemented in VLSI systems by taking the advantage of three-dimensional routing.