Bit-parallel Architecture Research Articles

A low complexity bit parallel polynomial basis systolic multiplier for general irreducible polynomials and trinomials

The bit parallel multiplication scheme is characterized by an important feature called concurrency, which makes its execution faster. The output through this scheme is generated in every clock cycle, after taking ‘m’ clock cycles in the beginning. In this paper, a polynomial basis systolic multiplier over irreducible polynomials (xm+tm−1xm−1+....t2x2+t1x1+t0) in GF(2m) is designed specifically for odd ‘m’, which takes ‘m’ clock cycles and this is further, used to design the low complexity bit-parallel architecture for general irreducible polynomials and trinomials (xm+xk+1). The area complexity of the proposed multiplier for general irreducible polynomials matches with the best existing multiplier with a 17% reduction in time complexity due to a considerable decrease in critical path delay. To the best of our knowledge, the area-delay product of the proposed multipliers is the lowest achieved when compared with the best multipliers available in the literature. FPGA implementation results also show that the proposed multiplier has 59% less space complexity and 47% less time complexity than the best-reported multiplier for m = 233.

Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures

This paper presents signal processing methods to enhance the energy vs. accuracy trade-off of in-memory computing (IMC) architectures. First, an optimal clipping criterion (OCC) for signal quantization is proposed in order to minimize the precision of column analog-to-digital converters (ADCs) at iso-accuracy. For a Gaussian distributed signal, the OCC is shown to reduce the column ADC precision requirements by 3 bits at an signal-to-quantization noise ratio (SQNR) of 22.5 dB over the commonly used full range (FR) quantizer. Next, the input-sliced weight-parallel (ISWP) IMC architecture is presented as a generalization of the popular bit-serial bit-parallel (BSBP) architecture. Quantization noise analysis of the ISWP indicates that its accuracy is comparable to BSBP while providing an order-of-magnitude reduction in energy consumption due to fewer array invocations and smaller ADC precision. Combining OCC and ISWP noise analysis, we map popular DNNs such as VGG-9 (CIFAR-10), ResNet-18 (CIFAR-10), and AlexNet (ImageNet) on a OCC-enabled ISWP architecture and show a reduction in energy consumption by an order-of-magnitude at iso-accuracy over the BSBP architecture that employs FR-based ADCs.

Hardware acceleration of regular expression repetitions in deep packet inspection

Network Intrusion Detection Systems (NIDS) make extensive use of regular expressions (regexes) as attack signatures. Such expressions can be handled in hardware using a bit-parallel (BP) architecture based on the Glushkov non-deterministic finite automata (NFA). However, many expressions contain constrained {min, max} repetitions which first need to be unrolled so that they can be handled by the standard BP system. Such unrolling often leads to an excessive memory requirement which makes handling of such regexes unfeasible. This study presents a solution, based on the standard BP architecture, which incorporates a counting mechanism that renders unrolling unnecessary. As a result, many regexes, which were previously unsuitable for the standard BP system, can now be efficiently handled. Unlike many other approaches, this architecture is dynamically reconfigurable thanks to its memory, rather than logic, based engine. This is important as NIDS rule sets are regularly updated. It can also handle repetition of both single and multi-symbol sub-expressions.

Pattern overlap in bit-parallel implementation of regular expression repetition quantifiers

Deep Packet Inspection DPI in Network Intrusion Detection and Prevention Systems NIDPS typically involves the matching of packet payloads against attack signatures in the form of regular expressions regexes. Existing research into the handling of the constrained {min, max} repetition syntax used in many regexes mainly proposes the use of a counting mechanism which avoids inefficient unrolling of the repeated sub-expression. However, many regexes cannot be handled as their format makes them susceptible to the problem of counter overlap. In this paper, we present a memory-centric bit-parallel hardware architecture that overcomes the issue of counter overlap through the use of a bit serial First-In-First-Out FIFO queue. The memory-centric rather than logic-centric nature of the design has the advantage of allowing dynamic updates to individual attack signatures. The solution proposed in this paper is targeted at ASIC and FPGA platforms and we present experimental results for a proof-of-concept design.

Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC

Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time constrains. However, such kind of architectures increase the area overhead and pin count, and therefore will not be suitable for area-constrained electronic consumer designs such as small portable multimedia devices. This paper addresses this problem by proposing two area efficient least significant bit (LSB) bit-serial architectures with small pin numbers. Both designs take advantage of data reusing technique in different ways for sum of absolute differences (SAD) computation and reading reference pixels, leading to a considerable reduction of memory bandwidth. The first architecture propagates the partial SAD and sum results and broadcasts the reference pixel rows whereas the second design reuse the SAD of small blocks and has a reconfigurable reference buffer leading to a better memory bandwidth when using hardware parallelism. The proposed designs benefit from several optimization techniques including an efficient serial absolute difference architecture, word length reduction by parallelism, bit truncation, mode filtering, and macroblock (MB) level subsampling, which significantly enhance their performances in terms of silicon area, throughput, latency, and power consumption. The first and second designs can support full search VBSME of 720?×?480 video with 30 frames per second (fps), two reference frames, and [?16, 15] search range at a clock frequency of 414 MHz with 29.28 k and 31.5 k gates, respectively.

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension

This paper presents four novel area-efficient field-programmable gate-array (FPGA) bit-parallel architectures of finite impulse response (FIR) filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. The key to this is a clever use of variable-depth shift registers which are efficiently implemented in Xilinx FPGAs in the form of shift register logic (SRL) components. Comparisons with the conventional architecture of FIR filter with symmetric boundary processing show considerable area saving especially with long-tap filters. For instance, our architecture implementation of the 8-tap low Daubechies-8 FIR filter achieves ~ 30% reduction in the area requirement (in terms of slices) compared to the conventional architecture while maintaining the same throughput. Two of the above-cited novel architectures are dedicated to the special case of symmetric FIR filters. The first architecture is highly area-efficient but requires a clock frequency doubler. While this reduces the overall processing speed (to a maximum of 2), it does maintain a high throughput. Moreover, this speed penalty is cancelled in bi-phase filters which are widely used in multirate architectures (e.g., wavelets). Our second symmetric FIR filter architecture saves less logic than the first architecture (e.g., 10% with the 9-tap low Biorthogonal 9&7 symmetric filter instead of 37% with the first architecture) but overcomes its speed penalty as it matches the throughput of the conventional architecture.

Concurrent Error Detection in Montgomery Multiplication over GF(2m)

Because fault-based attacks on cryptosystems have been proven effective, fault diagnosis and tolerance in cryptography have started a new surge of research and development activity in the field of applied cryptography. Without magnitude comparisons, the Montgomery multiplication algorithm is very attractive and popular for Elliptic Curve Cryptosystems. This paper will design a Montgomery multiplier array with a bit-parallel architecture in GF(2m) with concurrent error detection capability to protect it against fault-based attacks. The robust Montgomery multiplier array with concurrent error detection requires only about 0.2% extra space overhead (if m = 512 is as an example) and requires four extra clock cycles compared to the original Montgomery multiplier array without concurrent error detection.

Hardware-efficient systolic architectures for inversion in GF(2m)

We propose in-place systolic bit-serial, bit-parallel, and folded bit-parallel architectures for inversion in GF(2m). Our bit-serial architectures have the highest throughput 1/m of the three types but use more hardware than the other two types. Our bit-parallel architectures have throughput of 1/(2m − 1) with interleaved inputs and 1/(4m − 2) without interleaving. The new bit-serial and bit-parallel architectures proposed have the same throughput and latency but smaller hardware cost and shorter critical path delay than the best comparable architectures proposed previously. We also propose novel folded versions of our bit-parallel architectures which achieve 1/(4m − 2) non-interleaved throughput with even less hardware than our bit-parallel architectures. To the best of our knowledge, no comparable scheme has been proposed previously. The circuitry in each cell of our bit-serial architectures and the (folded and unfolded) bit-parallel architectures with distributed ring counters is the same for all values of m. Since there are no global control or data signals either, these architectures have excellent scalability properties and are very suitable for applications where m is large or variable. Implementation details using the TSMC Avanti 0.18 µm CMOS standard cell library are provided.

Bit-Parallel Arithmetic Implementations over Finite Fields GF(2 m ) with Reconfigurable Hardware

Galois (or finite) fields are used in a wide number of technical applications, playing an important role in several areas such as cryptographic schemes and algebraic codes, used in modern digital communication systems. Finite field arithmetic must be fast, due to the increasing performance needed by communication systems, so it might be necessary for the implementation of the modules performing arithmetic over Galois fields on semiconductor integrated circuits. Galois field multiplication is the most costly arithmetic operation and different approaches can be used. In this paper, the fundamentals of Galois fields are reviewed and multiplication of finite-field elements using three different representation bases are considered. These three multipliers have been implemented using a bit-parallel architecture over reconfigurable hardware and experimental results are presented to compare the performance of these multipliers.

Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., area–time product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-μm CMOS design rule showed that the delay time of multioperand multiplications-additions and the area–time product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture. © 1999 Scripta Technica, Syst Comp Jpn, 30(12): 43–51, 1999

Design of a reconfigurable VLSI processor for robot control based on bit‐serial architecture

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., area–time product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-μm CMOS design rule showed that the delay time of multioperand multiplications-additions and the area–time product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture. © 1999 Scripta Technica, Syst Comp Jpn, 30(12): 43–51, 1999

A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks

Wavelength division multiplexing (WDM) is emerging as a viable solution to reduce the electronic processing bottleneck in very high-speed optical networks. A set of parallel and independent channels are created on a single fiber using this technique. Parallel communication utilizing the WDM channels may be accomplished in two ways: (i) bit serial, where each source-destination pair communicates using one wavelength and data are sent serially on this wavelength; and (ii) bit parallel, where each source-destination pair communicates using a subset of channels and data are sent in multiple-bit words. Three architectures are studied in the paper: single-hop bit-serial star, single-hop bit-parallel star, and multi-hop bit-parallel shufflenet. The objective of this paper is to evaluate these architectures with respect to average packet delay, network utilization, and link throughput. It is shown that the Shufflenet offers the lowest latency but suffers from high cost and low link throughput. The star topology with bit-parallel access offers lower latency than the bit-serial star, but is more expensive to implement.

GF(2m) multiplication over triangular basis for design of Reed-Solomon codes

Bit-serial and bit-parallel multiplication architectures for GF(2m) are presented, using a triangular basis representation of field elements. The paper is a development of the work originally presented by Hasan and Bhargava. It is shown that, by forcing these multipliers to operate entirely over the triangular basis, lower latency delays and hardware savings can be made. Also, a more flexible definition of the triangular basis is presented, which allows a number of triangular bases to any given basis to be defined. It is shown that when the defining irreducible polynomial is a trinomial, the triangular basis is a simple permutation of the polynomial basis elements. Furthermore, if the defining irreducible polynomial is a pentanomial of a certain form the triangular basis to polynomial basis conversion requires minimal hardware and a reordering of basis coefficients.

Finite field division based on recursive division algorithm and composite fields

A new division scheme for GF(2m) is presented This scheme is based on the recursive division algorithm and composite fields ofthe form GF(22n) (m = 2n). The new division scheme offers reduced time complexity ofapproximately O(2n) when compared to traditional bit-serial architectures with O(22n). The scheme also offers lower hardware requirements when compared to bit-parallel architectures. The circuit architecture presented supports implementation in VLSI systems due to its regular and hardware efficient structures and is therefore suited to the implementation of Reed-Solomon codecs.

A novel high-speed bit-parallel multiply-accumulate arithmetic architecture employing mixed SB/TC number arithmetic

A novel high-speed bit-parallel multiply-accumulate arithmetic architecture employing mixed SB/TC number arithmetic

VLSI implementation of digit-serial arithmetic modules

This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach.

Silt: A distributed bit-parallel architecture for early vision

A new form of parallelism,distributed bit-parallelism, is introduced. A DBP organization distributes each bit of a data item to a different processor. DBP allows computation that is sublinear with word size for such operations as integer addition, arithmetic shifts, and data moves. The implications of DBP for system architecture are analyzed. An implementation of a DPB architecture based on a mesh with a fost-bypass network is presented, and the performance of DBP algorithms on this architecture is analyzed. The application of the architecture to early vision algorithms is discussed.

A systematic approach for design of digit-serial signal processing architectures

A systematic unfolding transformation technique for transforming bit-serial architecture into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed. >

An efficient two's complement systolic multiplier for real-time digital signal processing

The authors propose a fast, area-efficient, bit-parallel systolic architecture for two's complement multiplication, which can be implemented on a single VLSI chip. This architecture is more efficient than other reported bit-parallel architectures in terms of performance and utilization of silicon area. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are employed on the cell level instead of a basic full adder, which increases the throughput rate by a factor of three over the other reported pipeline structures. The structure is highly regular and programmable, and it can be adapted to the requirements of different digital signal processing applications without significant loss in throughput and efficiency. >

Advanced serial-data computation

Serial-data architectures are generally known, but little used in comparison to bitparallel architectures in realization of high-performance computer arithmetic. This is mostly due to perceived limitations in the serial-data approach, such as fixed word size, slow throughput, domination of pipelining latches, and functional paucity. This paper catalogs recent advances in the art of serial-data architectural design, which directly address these limitations. A range of powerful computational modules is introduced, using symmetric-coded distributed arithmetic to provide area savings, multiwire techniques to allow variations in throughput and/or dynamic range, and digiton-line techniques for more advanced arithmetic operations. The additional flexibility afforded to designers as a consequence prompts a reexamination of many applications which are presently best served by bit-parallel architectures.