Bitline Leakage Research Articles

Design of 65nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

In this paper we present a 0.25-1.0V, 0.1-200MHz, 256×32, 65nm SRAM macro. The main design techniques include a bitline leakage prediction scheme and a non-trimmed non-strobed sense amplifier to deal with process and runtime variations and data dependence.

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements

Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs). These code-dependent read noises are primarily due to the charge-sharing effect, bitline leakage current, and crosstalk between bitlines, which become worse at lower VDD. This study proposes a dynamic split source-line (DSSL) scheme for NAND-ROM. The proposed scheme overcomes code-dependent read noises while improving the read access time and suppressing the active-mode gate leakage current, with only a 1% area penalty in the cell array. Experiments on a fabricated 256 Kb macro using a 90 nm industrial logic process demonstrate that the proposed DSSL scheme achieves 100% code-pattern coverage under a small sensing margin. Additionally, the DSSL NAND-ROM works with a wide range of supply voltages (1-0.31 V) with a 38%, 45.8%, and 37% improvement in speed, power, and standby current, respectively, at VDD = 1 V.

A Low-Power Register File with Dual-VtDynamic Bit-Lines driven by CMOS Bootstrapped Circuit

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a 256×40-bit register file incorporating dual-V t bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

Wide $V_{\rm DD}$ Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems

Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage, and temperature conditions. The DMST technique employs a single replica column and new dummy cells to track both precharge and sensing activities in asynchronous SRAM, with bitline leakage considered. The DMST-technique simulation uses both 65-nm and 0.35-mum technologies. Several 0.35-mum DMST SRAM macros were fabricated in a test chip and embedded in a mass-produced system-on-a-chip suitable for various battery/supply-voltage configurations. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths and offers the same area overhead as conventional sense-tracking-only replica-column schemes.

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of 6T).

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 muA bit-line leakage current.

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies or affect performance and gate-oxide reliability. In this paper, we propose application of a specific carbon nanotube (CNT)-based nano-electromechanical switch as a leakage-control structure in logic and memory circuits. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving the read noise margin as well. Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold CMOS technique. In memory circuits, simulations show reduction in standby leakage and reduction in bitline leakage compared with the best existing techniques.

Reliability of erasing operation in NOR-Flash memories

The erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging).

Optimizing Leakage Energy Consumption in Cache Bitlines

As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy is critical as well. To this end, we propose a predictive precharging scheme to reduce bitline leakage energy consumption. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.

A 6-GHz 16-kB L1 cache in a 100-nm dual-v t technology using a bitline leakage reduction (blr) technique

This work describes an aggressive SRAM cell configuration using dual-V/sub T/ and minimum channel length to achieve high performance. A bitline leakage reduction technique is incorporated into an L1 cache design using the new cell in a 100-nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6-GHz operation at with 15% higher energy.

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.

Low-Voltage and Low-Current Flash Memory Using Source Induced Band-to-Band Tunneling Hot Electron Injection to Perform Programming

A novel n-channel flash memory cell, which uses source induced band-to-band hot electron injection (SIBE) to perform programming, is proposed in this paper. With the proposed programming method, the drain voltage and the control gate voltage can be reduced to as low as -3.6 V and 10 V with the assistance of the source voltage, and the programming speed can increase up to 10 µs. Moreover, the programming current is reduced to approximately 3.0 µA, and a large read current of 64 µA is also realized. The simulation and the testing results show that the proposed flash cell features low programming voltage, low power, high programming efficiency, high read current, low bit-line leakage current, and good reliability.

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V/sub TH/) of the transistors is reduced for high performance at low power-supply voltage (V/sub DD/). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-/spl mu/A bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V/sub TH/, and keeps the V/sub TH/ and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-/spl mu/m CMOS technology, which demonstrates the effectiveness of the scheme.