Bit Length Research Articles

Electronic document authentication

Digital signature techniques such as the Rivest-Shamir-Adleman (RSA) scheme can be used to establish both the authenticity of a document and the identity of its originator. However, because of the computationally-intensive nature of the RSA algorithm, most digital signature schemes make use of a checksum technique to summarize or represent the document, and then digitally sign the checksum. Message authentication codes (MACs), based on the Data Encryption Standard (DES), are often used for this purpose. It is shown that cryptographic checksums that are intended to detect fraudulent messages must be on the order of 128 bits in length, and the ANSI X9.9-1986 message authentication standard is criticized on that basis. In addition, architectural arguments are advanced to illustrate the advantages of a checksum algorithm that is not based on the use of cryptography and does not require the use of a secret key. Manipulation detection codes (MDC) are defined as a class of checksum algorithms that can detect both accidental and malicious modifications of an electronic message or document, without requiring the use of a cryptographic key.

Design of a 90° 12 GHz faraday rotator polariser using a cavity technique

Ferrite devices based on Faraday rotation remain of interest at both microwave and millimeter wavelengths. Although a complete mathematical description of ferrite cylinders in round waveguides is available, the experimental verification of rotation or differential phase shift in a round waveguide is not simple. The paper describes a resonant cavity procedure which permits the evaluation of the two propagation constants in such a magnetised waveguide. It is obtained by incorporating the Faraday rotator section into a resonator structure by closing both ends of the waveguide and separately tuning its length for each of the two split branches of the magnetised resonator to the frequency of the demagnetised one. The paper includes a lower bound on the length of the rotator bit (or an upper bound on the splitting between the phase constants) in terms of the directivity of the section.

Document retrieval using a serial bit string search

An experimental best match retrieval system is described based on the serial file organisation. Documents and queries are characterised by fixed length bit strings and the time-consuming character-by-character term match is preceeded by a bit string search to eliminate large numbers of documents which cannot possibly satisfy the query. Two methods, one fully automatic and one partially manual in character, are described for the generation of such bit string characterisations. Retrieval experiments with a large document test collection show that the two-level search can increase substantially the efficiency of serial searching while maintaining retrieval effectiveness, and that a single-level search based only upon the bit strings results in only a small decrease in effectiveness in some cases.

Drilling Now

Drilling Now

Thoth, a portable real-time operating system (Extended Abstract)

Thoth is a portable real-time operating system which has been developed at the University of Waterloo. Various configurations of Thoth have been running since May 1976; it is currently running on two minicomputers with quite different architectures (Texas Instruments 990 and Data General NOVA). This research is motivated by the difficulties encountered when moving application programs from one system to another; these difficulties arise when interfacing with the hardware and support software of the target machine. The problems encountered interfacing with the new software support are usually more difficult than those of interfacing with new hardware because of the wide variety of abstract machines presented by the compilers, assemblers, loaders, file systems and operating systems of the various target machines. We have taken the approach of developing portable system software and porting it to “bare” hardware. Because the same system software is used on different hardware, the same abstract machine is available to application programs. Thus most application programs which use Thoth can be portable, if not machine independent. Most previous work on software portability has focused on problems of porting programs over different operating systems as well as hardware. To our knowledge, this is the first time an entire system has been ported. Our experience indicates that this approach is practical both in the cost of porting the system and its time and space performance. The design of Thoth strives for more than portability. A second design goal is to provide a system in which programs can be structured using many small concurrent processes. Thus we have aimed for efficient interprocess communication to make this structuring technique attractive. We have also provided safe dynamic process creation and destruction. A third design goal is that the system meet the demands of real-time applications. To meet this goal, the system guarantees that the worst-case time for response to certain external events (interrupt requests) is bounded by a small constant. A fourth design goal is that the system be adaptable to a wide range of real-time applications. A range of system configurations is possible: A stand-alone application program can use a stripped version of the Thoth kernel which supports dynamic memory allocation and interprocess communication. Such a configuration requires less than 2000 16-bit words of memory. Larger configurations can support process destruction, a device-independent input-output system, a tree-structured file system, and multiple teams of processes. (A team is a set of processes which share the same logical address space and therefore can share data.) Thoth is implemented in a high-level language called Eh (a descendant of BCPL) and a small amount of assembly language. The major job in porting the system seems to be in redesigning the code generation parts of the compiler. Since it appears impractical to design system software to be portable over all computers (even over all existing machines), we have aimed at making Thoth portable over a subset of machines. Machines in the set can be characterized by a set of properties such as: a word must be at least 16 bits in length, a pointer to a word must fit into a word, etc. Roughly, this set of machines includes most modern minicomputers. It is important that many machines which do not yet exist will be included in it. A number of application programs have been written using Thoth. In addition to software development tools, communications and real-time control programs have been written. All of these programs require few if any changes when ported to new hardware. Some of these programs have been developed by inexperienced programmers who were not planning on porting their program. Hence, it seems to take less skill to write portable software in this system than using conventional techniques. However, existing software written for other systems is incompatible with Thoth and usually difficult to port to the Thoth system. Although, at the time of this writing, we have limited experience with porting the system to new hardware, we feel that Thoth has been highly successful in terms of our original objectives. Among other things, it has partially demonstrated the feasibility of building a portable operating system for a specified class of machines.

A parametric associative memory emulation

An experimental associative memory facility has been created by microprogramming a conventional computer. The microprogramming was done by expansion of an IBM 1130 emulation that was microcoded on a Digital Scientific Corporation META 4 computer. The associative memory (AM), as seen by the 1130 applications programmer, is an integral part of the computer with 54 machine instructions provided for its control and use.The structural characteristics of the apparent associative memory are parametrically defined to the emulation via a special SETUP command. This command may occur repeatedly within a program to dynamically alter the AM's characteristics or, indeed, to provide several different AM's. The characteristics that may be specified include the cell width (W) in 16-bit word increments, the number of cells (N), the locations in core memory to be used by the AM and its associated registers, and the memory protect status of these memory locations. The parameters are maintained in a fast scratch-pad memory, whence they are employed to control the AM emulation.Three pseudoregisters are used by the associative memory: (1) a data register (DR), which can hold the contents of one cell (i. e., W bits in length); (2) a response register (RR) N bits in length; and (3) an availability register (AR), also N bits in length.The data register provides the primary interface between the AM and the 1130 program. The response register is employed to indicate which cells in the AM have responded to a given search command. The availability register is used to indicate which cells are empty (or available) and which are to be considered whenever a search command is executed. The AM can be addressed either conventionally or associatively.The commands provided to utilize the AM fall into five categories: (1) register commands to manipulate the DR, RR, and AR; (2) fetch and store commands to store and retrieve information; (3) search commands to compare a given argument against the AM; (4) field-to-field search commands that compare two fields within each cell; and (5) test and branch instructions. Field specifications for search commands are defined through the use of pointer and length information contained within the command.Communication with the AM is via the DR. Search arguments and data to be stored are placed there, as are data retrieved from the AM. Searches permitted include match, no match, less than, less than or equal to, greater than, greater than or equal to, next lower, next greater, minimum, and maximum.The commands themselves, viewed as 1130 operators, may occupy either one, two, or three machine words, depending upon the operation, and may contain an address, one or two pointer specifications, one or two length specifications, a reset flag, or an immediate value, as required. Indexing is permitted for those operations having an address. The code-cracking mechanism of the 1130 emulation is used but is augmented to handle the three-word instructions. Microsubprograms are then executed for each emulated instruction or class of instructions.The META 4 computer on which the AM system was implemented is a flexible, logical processor that is controlled by an easily modified, random-access, read-only memory (ROM). Up to 32 general-purpose registers may be employed, together with three data buses (two source and one destination), an arithmetic-logical unit, and a shifter unit. Control is exercised at the gate level via microcode commands, 32 bits in length, in the ROM. Core memory is treated essentially as a peripheral with access via a pair of registers, one for data and the other for address information. The usual complement of peripherals, card readers, printers, disks, etc., may be attached.The basic hardware configuration required for 1130 emulation on a META 4 consists of 8K main-core memory, 2K read-only memory, and 20 registers. This configuration was augmented for the AM emulation by the addition of 8K more core, 2K additional ROM, two additional registers, two scratch-pad memories of 64 words each, and a set of internal timers to provide timing information on application programs.Several applications have been programmed in both a conventional manner and by using the associative memory capability in order to obtain relative timing information. One such application, a personnel file information storage and retrieval system, has provided a speed advantage of as much as 10 to 1 when the AM is employed. Building on the AM capability, a set of macroinstructions was developed to provide an apparent associative processor. Several matrix manipulation routines were developed using this facility, and these routines also exhibited a significant speed advantage over their conventionally programmed counterparts.

Correction of errors in multilevel Gray coded data

In this paper we present a new error-control technique intended for use in 2^l -level data-transmission systems that employ Gray coding to transform a binary source sequence into the 2^l -ary transmitted sequence. The codes, which we call i -compressed codes, make use of the structure of binary codes and have the property that for some integer i , 1 \leq i \leq l , transmission errors can be corrected if the erroneously received signals lie less than 2^{i-1} levels from the corresponding correct, or nominal signal levels. The number of such errors that can be corrected is related to the error-correcting capability of the underlying binary code used in the construction. In return for this restriction on the magnitude of correctable errors in the received signal, these codes have higher rates than binary codes of comparable length (in bits) and number of correctable errors. Hence in applications where it can be assumed that the fraction of errors exceeding a certain magnitude is negligible (or at least tolerable), this technique is more efficient than the conventional practice of placing a binary encoder between the data source and modulator and a binary decoder between the demodulator and data sink. Furthermore, although the i -compressed codes are nonbinary, the decoding algorithm is that of the underlying binary code plus a small amount of additional processing; hence it is generally simpler to implement than other nonbinary decoding algorithms. It is also observed that the rate of an i -compressed code is always greater than that of the underlying binary code. Thus certain classes of low-rate binary codes that have simple decoding algorithms can be used as underlying codes in the construction of high-rate easily decodable i -compressed codes. Finally, for the case i = 1 , encoding and decoding becomes exceptionally simple and for this case it is possible to make use of soft decisions at the receiver to improve the performance.

Design of large high-speed floating-point-arithmetic units

An investigation of the design philosophy of large floating-point -arithmetic units has been undertaken, with a view to establishing the principles for constructing such a unit for a large high-speed computing system. The main consideration applied was maximum speed for a reasonable cost in a machine handling numbers 30–64 bits in length. Consideration of compatibility with other systems was specifically excluded, although the unit to be implemented does take this factor into account. Within these constraints, it is shown that negative numbers should be represented in twos-complement form. Numbers of upto 64 bits in length would be handled, with the binary point at the less significant end of the mantissa. Rounding should be performed by forcing a ‘carry in’ to the least significant bit when the answer is more than single length, sufficient information being retained to enable multilength arithmetic to be implemented. Answers should not be normalised. The data presented are sufficient to indicate the effect of applying different criteria.

Representing characters to computers

AbstractInformation systems requiring special, extended character sets and/or special input/output devices require special attention to character representation (CR). Three CR's are usually involved: input, storage, and output. The storage CR is central, and system designers should plan it carefully to minimize storage space, program complexity, and execution time. Plans should include consideration of provisions for future expansion of the character set and/or change in I/O devices. Approaches to CR can be with fixed or variable length bit strings on binary machines. This paper delineates six different CR methods and discusses attributes of each in relation to information system requirements.

The SDP-1 Stored-Program Computer

A stored-program computer could be used to advantage on small scientific spaeeraft because of its flexibility. This paper describes the design and programming of a stored-program computer specifically adapted to this particular application. In order to be suitable for use in a small scientific spacecraft, a computer must have the following characteristics: reliability, low power drain, light weight, small size, problem-solving power, and flexibility. To meet these requirements, a computer was designed that has 1024 words of program memory and 512 words of data memory. The words are 12 bits in length and both memories are randomly accessed. In order to protect the program, the program memory is of the nondestrutive read-out type. The data memory is the conventional read/write variety. The computer is organized such that the power drain is small and less hardware is required by restricting parallel gating of information, number of registers, and number and complexity of instructions. Considerable effort has been devoted to programming the computer. Analysis shows that it takes on the order of two milliseconds to perform one of the floating-point operations. These limitations should be acceptable; the computer is not expected to be required to perform extremely complex or lengthy computations.

The Synthesis of Binary Sequence Detectors

Abstract—A method is presented for synthesizing a sequential network for detecting a given n-place nonperiodic binary sequence within a data stream. The n-place nonperiodic sequence is characterized as a binary (n, r) ring sequence. The state assignment for r 2-state memory elements is determined from an ordered set of n distinct subsequences r bits in length. The minimization of r simultaneous Boolean functions of r+l variables yields a representation of internal combinational logic in two-level form.