Bit-flipping Decoding Research Articles

Two-Round Selection-Based Bit Flipping Decoding Algorithm for LDPC Codes

This paper presents a novel iterative reliability-based bit flipping (BF) algorithm for decoding low-density parity-check codes. The new decoder is a single BF algorithm called two-round selection -based bit flipping. It introduces the idea of a two-round selection of the flipped bit, based successively on hard and soft received channel values. In the first stage, a set of unreliable bits is identified, and then a second selection is used, to pick out among them the bit to flip. In the second round of selection, the initial belief about received signals, contributes efficiently to selecting the best candidate bit. We demonstrate through simulations over the binary-input additive white Gaussian noise channel and the Rayleigh fading channel that the proposed algorithm exhibits better decoding performance when compared with some well-known soft decision BF algorithms. A complexity analysis of the proposal and a comparison to other BF decoders are also presented.

The Syndrome Bit Flipping Algorithm for LDPC Codes

Performance of LDPC decoders at high SNR is dominated by trapping sets that induce an error floor in the performance curve. We propose a new algorithm that resolves trapping sets and lowers the error floor. The new algorithm, called Syndrome Bit Flipping (SBF), computes the sum of adjacent parity violations at each symbol node. Bits are flipped by comparing the syndrome sum against a time-varying threshold called the decoding key. SBF is compared to other bit-flipping decoders on the Binary Symmetric Channel (BSC), and is demonstrated as a post-processing step for a Noisy Gradient Descent Bit-Flipping (NGDBF) hardware decoder. We demonstrate the post-processing method for an LDPC code defined in the 802.3an standard, and find that the frame error rate is improved by at least two orders of magnitude, even as the required iterations are reduced by 33%.

Adaptive Gradient Descent Bit-Flipping Diversity Decoding

In this letter we propose a novel framework for designing decoders, for Low-Density Parity Check (LDPC) codes, that surpasses the frame error rate performance of Belief-Propagation (BP) decoding on binary symmetric channels. Its key component is the adaptation method, based on the genetic optimization algorithm, that is incorporated into the recently proposed Gradient Descent Bit-Flipping Decoding with Momentum (GDBF-w/M). We show that the resulting decoder outperforms all state-of-the-art probabilistic bit-flipping decoders and, additionally, it can be trained to perform beyond BP decoding, which is verified by numerical examples that include codes used in IEEE 802.3an and 5GNR standards. The proposed framework provides a systematic method for decoder optimization without requiring knowledge of trapping sets. Moreover, it is applicable to both regular and irregular LDPC codes.

Higher-Order Belief Propagation Correction Decoder for Polar Codes.

Belief propagation (BP) decoding for polar codes has been extensively studied because of its inherent parallelism. However, its performance remains inferior to that of successive cancellation list decoding (SCL) due to the structure of the decoding graph. To improve the block error rate (BLER) performance, the BP correction (BPC) decoding, a post-processing scheme that corrects prior knowledge of the identified code bit, improves convergence by executing additional iterations on the failed BP decoder. Moreover, the BPC decoder demonstrates a better decoding performance than the BP-based bit-flipping decoder. Nevertheless, the additional decoding attempts lead to increased latency. In this article, a modified BPC decoder is proposed to reduce the number of decoding attempts by redefining the correction rules. A new metric is designed to effectively identify the corrected location. Numerical results show that the proposed modified BPC decoder achieves a slight improvement in BLER compared with the original BPC, with a dramatic reduction in average complexity. Furthermore, a higher-order version, named MBPC-, is extended to further improve the performance, where the is the maximum correction order. Numerical results show that the higher-order modified BPC achieves a similar BLER performance to existing multiple bit-flipping BP decoders but has around half the latency overhead. In addition, the proposed MBPC-2 decoder performs better than the cyclic redundancy check-aided SCL (CA-SCL) decoder with list size 4 and is slightly worse than the CA-SCL with list size 8 in high signal-to-noise ratio (SNR) regions but with significant decoding latency reduction.

A Low-Latency BF Decoding of LDPC Codes With Dynamic Thresholds

This letter proposes a high throughput bit-flipping (BF) algorithm for regular LDPC codes with dynamic thresholds. In the iterative decoding, the flipping threshold is dynamically updated according to the previous flipping results. Compared to the exiting hard-information-based BF algorithms, the proposed algorithm can get better decoding performance. At the same time, in order to accelerate the convergence speed, we limit the number of occurrences of high thresholds which effectively reduces the invalid decoding iterations. The proposed algorithm has better decoding performance and lower average number of iterations which is suitable for the flash storage systems with low latency and high throughput requirements.

On the modification of bit-flipping decoder of LDPC-codes

Introduction. In all types of digital communication, error control coding techniques are used. Many digital communication standards, such as Wi-Fi and 5G, use low density parity check (LDPC) codes. These codes are popular because they provide building encoders and decoders with low computational complexity. This work objective is to increase the error correcting capability of the well-known bit-flipping decoder (BF) of LDPC-codes. For this purpose, a modification of the decoder is built, which enables to dynamically control one of its main parameters whose choice affects significantly the quality of decoding. Materials and Methods. The well-known bit-flipping decoder of binary LDPC-codes is considered. This decoder has several parameters that are not rigidly bound with the code parameters. The dependence of the decoding quality on the selection of the output parameters of the bit-flipping decoder was investigated through simulation modeling. It is shown that the decoding results in this case are significantly affected by the input parameter of the decoder — threshold T. A modification of the BF-decoder of binary LDPC-codes has been developed, in which it is proposed to set the threshold dynamically during the execution of the algorithm depending on the error rate. A comparative analysis of the error- correcting capability of decoders is carried out by the simulation modeling method. Results. A lemma on the maximum value of the decoder threshold T is formulated and proved. Upper bounds for the number of operations are found for the original and modified decoders. A simulation model that implements a digital noise-immune communication channel has been built. In the model, the initial data is encoded with a given LDPC-code, then it is made noisy by additive uniformly distributed errors, and thereafter, it is decoded in turn by the bit-flipping algorithm with different threshold T parameters, as well as by a modified decoder. Based on the input and output data, the correction capacity of the decoders used is estimated. Experiments have shown that the error-correcting capability of the modified decoder in the range of the real error rate is higher than that of the original decoder, regardless of the selection of its parameters. Discussion and Conclusions. The lemma, proved in the paper, sets the upper bound on the threshold value in the original decoder, which simplifies its adjustment. The developed modification of the decoder has a better error- correcting capability compared to the original decoder. Nevertheless, the complexity of the modification is slightly increased compared to the original algorithm. It has been pointed out that the decoding quality of a modified decoder develops with a decrease in the number of cycles in the Tanner graph and an increase in the length of the code.

An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder.

Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.

Reduced complexity hard‐ and soft‐input BCH decoding with applications in concatenated codes

Error correction coding for optical communication and storage requires high rate codes that enable high data throughput and low residual errors. Recently, different concatenated coding schemes were proposed that are based on binary BCH codes with low error correcting capabilities. In this work, low-complexity hard- and soft-input decoding methods for such codes are investigated. We propose three concepts to reduce the complexity of the decoder. For the algebraic decoding we demonstrate that Peterson's algorithm can be more efficient than the Berlekamp–Massey algorithm for single, double, and triple error correcting BCH codes. We propose an inversion-less version of Peterson's algorithm and a corresponding decoding architecture. Furthermore, we propose a decoding approach that combines algebraic hard-input decoding with soft-input bit-flipping decoding. An acceptance criterion is utilised to determine the reliability of the estimated codewords. For many received codewords the stopping criterion indicates that the hard-decoding result is sufficiently reliable, and the costly soft-input decoding can be omitted. To reduce the memory size for the soft-values, we propose a bit-flipping decoder that stores only the positions and soft values of a small number of code symbols. This method significantly reduces the memory requirements and has little adverse effect on the decoding performance.

Reinforcement Learning for Bit-Flipping Decoding of Polar Codes

A traditional successive cancellation (SC) decoding algorithm produces error propagation in the decoding process. In order to improve the SC decoding performance, it is important to solve the error propagation. In this paper, we propose a new algorithm combining reinforcement learning and SC flip (SCF) decoding of polar codes, which is called a Q-learning-assisted SCF (QLSCF) decoding algorithm. The proposed QLSCF decoding algorithm uses reinforcement learning technology to select candidate bits for the SC flipping decoding. We establish a reinforcement learning model for selecting candidate bits, and the agent selects candidate bits to decode the information sequence. In our scheme, the decoding delay caused by the metric ordering can be removed during the decoding process. Simulation results demonstrate that the decoding delay of the proposed algorithm is reduced compared with the SCF decoding algorithm, based on critical set without loss of performance.

Error Correction LDPC Encoder with Bit-Flipping Decoder

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

Information Storage Bit-Flipping Decoder for LDPC Codes

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information storage bit-flipping (ISBF) decoder to solve this problem. Different from the existing bit-flipping (BF) decoders which adopt serial decoding manner, in the ISBF decoder, by storing the previous decoding information, the global maximum-finding operation can be executed in parallel to other decoding operations, significantly shortening the critical path. Moreover, a nonuniform flipping rule is incorporated to achieve a better decoding performance. We also present an efficient architecture to implement the ISBF decoder. The design example demonstrates that compared to other hard-decision BF decoders, the ISBF decoder could provide both the best decoding performance and throughput on BSC.

Analysis of the Error Correction Capability of LDPC and MDPC Codes Under Parallel Bit-Flipping Decoding and Application to Cryptography

Iterative decoders used for decoding low-density parity-check (LDPC) and moderate-density parity-check (MDPC) codes are not characterized by a deterministic decoding radius and their error rate performance is usually assessed through intensive Monte Carlo simulations. However, several applications, like code-based cryptography, need guaranteed low values of the error rate, which are infeasible to assess through simulations, thus requiring the development of theoretical models for the error rate of these codes. Some models of this type already exist, but become computationally intractable for parameters of practical interest. Other approaches approximate the code ensemble behaviour through assumptions, which may not hold true for a specific code. We propose a theoretical analysis of the error correction capability of LDPC and MDPC codes that allows deriving tight bounds on the error rate at the output of parallel bit-flipping decoders. Special attention is devoted to the case of codes with small girth. Single-iteration decoding is investigated through a rigorous approach, which does not require any assumption and results in a guaranteed error correction capability for any single code. We show an example of application of the new bound to the context of code-based cryptography, where guaranteed error rates are needed to achieve strong security levels.

Network coding schemes with efficient LDPC coded MIMO–NOMA in two‐way relay networks

The combination of non-orthogonal multiple access (NOMA) and multi-input multi-output (MIMO) approaches has been considered as assuring multiple access for the fifth generation technology. In this study, the performance of a 2 × 2 MIMO–NOMA system with low-density parity check (LDPC) codes is investigated. Redundancy with randomly interleaved differential encoding (R-RIDE) is proposed and applied to LDPC encoded messages by two users. LDPC decoding is done using the sum-product algorithm (SPA), which has two types of decoding methods, hard-decision and soft-decision. For hard-decision, bit-flipping decoder is used and for soft-decision, probability domain, log-domain, and simplified log-domain decoders are used. Bit error rate (BER) versus signal-to-noise ratio (SNR) in (dB) and average mutual information (AMI) in (bps/Hz) versus SNR (dB) are evaluated to compare the performance of the proposed and conventional LDPC schemes in NOMA and MIMO–NOMA systems. Simulation results show that both AMI and BER of the proposed LDPC–R-RIDE in MIMO–NOMA system greatly outperforms conventional LDPC coded schemes in NOMA and MIMO–NOMA systems. Moreover, the proposed R-RIDE-LDPC in MIMO-NOMA system outperforms the proposed scheme in the NOMA system. From the simulation results, LDPC–R-RIDE with simplified log-domain decoder has the best AMI result and BER performance compared with other decoding methods.

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography

Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension.

Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

Multi-Stage Bit-Flipping Decoding Algorithms for LDPC Codes

We present two general multi-stage (MS) bit-flipping (BF) decoding algorithms for low-density parity-check (LDPC) codes. Both algorithms consist of soft-decision (SD) and hard-decision BF decoding parts. In comparison with known MS LDPC decoders, our approach is much simpler as all stages share the same BF structure. The only complexity increase is due to the use of an adaptive stage-switching (SS) mechanism which gives near-optimal SS timing. A new design issue we address is that the first-stage algorithm’s parameter has to be re-tuned to achieve the optimal overall performance. The numerical results demonstrate that the proposed decoding methods can significantly improve the error-rate performance of the conventional SD BF decoders.

High‐throughput Bit Flipping decoder for structured LDPC codes

Low-density parity-check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high-throughput parallel bit-flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite-geometry LDPC (FG-LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG-LDPC codes, respectively. Compared to the state-of-the-art design, the proposed designs offer 4 . 5 times higher normalised throughput.

Soft‐input bit‐flipping decoding of generalised concatenated codes for application in non‐volatile flash memories

Error correction coding based on soft-input decoding can significantly improve the reliability of non-volatile flash memories. This work proposes a soft-input decoder for generalised concatenated (GC) codes. GC codes are well suited for error correction in flash memories for high reliability data storage. The authors propose GC codes constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon (RS) codes. The extended BCH codes enable an efficient hard-input decoding. Furthermore, a low-complexity soft-input decoding method is proposed. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer RS codes, this acceptance criterion can improve the decoding performance and reduce the decoding complexity. The presented simulation results show that the proposed bit-flipping decoder in combination with outer error and erasure decoding can outperform maximum-likelihood decoding of the inner codes.

Low-Latency Adaptive Ordered Statistic Decoding of Polar Codes

Deploying polar codes in ultra-reliable low-latency communication (URLLC) is of critical importance and is currently receiving tremendous attention in both academia and industry. However, most of the state of the art polar codes decoders like progressive bit-flipping decoder (PBF) and successive cancellation list (SCL) decoder, involve strong data dependencies and suffer from huge decoding delay. This contradicts the low-latency requirement in URLLC. To address such issue, this paper appeals to the parallel computing and proposes an adaptive ordered statistic decoder (OSD). In particular, we first propose a novel codeword searching metric which proves to be hardware-friendly, and an adaptive OSD algorithm is then developed to adaptively rule out the unpromising codewords, thus significantly reducing the latency. Secondly, to further reduce the computational complexity of the proposed algorithm, we decompose the current code sequence into several independent subcodes, and by handling these subcodes with concatenated adaptive OSDs, a good trade-off between decoding latency and complexity can be achieved. Finally, numerical results show that the proposed adaptive OSD outperforms the conventional decoders in terms of block error rate (BLER) and decoding latency.

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

This paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in Section II . The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.