Bit-flipping Algorithm Research Articles

Unreliability normalization weighted bit-flipping algorithms of LDPC decoding for ReRAM systems

Unreliability normalization weighted bit-flipping algorithms of LDPC decoding for ReRAM systems

Two-Round Selection-Based Bit Flipping Decoding Algorithm for LDPC Codes

This paper presents a novel iterative reliability-based bit flipping (BF) algorithm for decoding low-density parity-check codes. The new decoder is a single BF algorithm called two-round selection -based bit flipping. It introduces the idea of a two-round selection of the flipped bit, based successively on hard and soft received channel values. In the first stage, a set of unreliable bits is identified, and then a second selection is used, to pick out among them the bit to flip. In the second round of selection, the initial belief about received signals, contributes efficiently to selecting the best candidate bit. We demonstrate through simulations over the binary-input additive white Gaussian noise channel and the Rayleigh fading channel that the proposed algorithm exhibits better decoding performance when compared with some well-known soft decision BF algorithms. A complexity analysis of the proposal and a comparison to other BF decoders are also presented.

An Improved Bit-Flipping Algorithm of Successive Cancellation List Decoding for Polar Codes

Polar codes, as the coding scheme for the control channel in fifth-generation mobile communication technology (5G), have attracted widespread attention since their proposal. As a mainstream decoding algorithm for polar codes, the successive cancellation list (SCL) decoder usually improves the error correction performance by increasing the list size, but this method suffers from the problems of high decoding complexity. To address this problem, this paper proposes a layered-search bit-flipping (LS-SCLF) decoding algorithm based on SCL decoding. Firstly, a new flip-bit metric is proposed, which derives a formula to approximate the probability of an error occurring in an information bit. This formula introduces a perturbation parameter to improve the calculation accuracy. Secondly, a compromise scheme for determining the perturbation parameter is proposed. The scheme uses Monte Carlo simulation to determine an optimized parameter for the precise positioning of the first erroneous decoded bit under different decoding conditions. Finally, a layered search strategy is adopted to sequentially search the erroneous decoded bits from the low order to high order, which can correct up to multiple bits at the same time. Simulation results show that the proposed algorithm achieves improved error correction performance with a slight increase in decoding complexity compared to the generalized SCL-Flip (GSCLF) decoding algorithm. This algorithm also achieves a good balance between the error correction performance and decoding complexity.

Design of Implicit Partial Product-LDPC Codes and Low Complexity Decoding Algorithm

In this letter, we are concerned with a recently proposed class of product codes, called implicit partial product low-density parity-check (IP-LDPC) codes, which consist of LDPC codes for rows and Bose-Chaudhuri-Hocquenghem (BCH) codes for columns. Distinguished from the conventional product codes, only partial columns are doubly-protected and the column checks are transmitted implicitly rather than explicitly. For any given LDPC code, we present three heuristic rules to design an IP-LDPC code with the same code rate, showing how to select the number of doubly-protected columns and the BCH code (for columns). The stringent constraint is that the product of the number of doubly-protected columns and the length of syndrome per column must be less than or equal to the product of the number of the rows and the length of extra bits that can be carried reliably and implicitly per row (LDPC codeword). We also propose a simple bit-flipping algorithm for the column decoding in the case when the number of unsuccessfully decoded rows is relatively small, which occurs often especially when the iterative decoding is implemented. The simulation results show that IP-LDPC codes can lower down the word error rate (WER) of a (3,6)-regular LDPC code with length 1024 from 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−6</sup> at the SNR around 2.0 dB but without any code rate loss.

Decoding of linear codes for single error bursts correction based on the determination of certain events

Introduction: In modern systems for communication, data storage and processing the error-correction capability of codes are estimated for memoryless channels. In real channels the noise is correlated, which leads to grouping error in bursts. A traditional method to fight this phenomenon is channel decorrelation, which does not allow developing of coding schemes, mostly utilizing the channel capacity. Thus the development of bursts decoding algorithms for arbitrary linear codes is the actual task. Purpose: To develop a single error burst decoding algorithm for linear codes, to estimate the decoding error probability and computational complexity. Results: Two approaches are proposed to burst error correction. The first one is based on combining the window sliding modification of well-known bit-flipping algorithm with preliminary analysis of the structure of parity check matrix. The second one is based on the recursive procedure of constructing the sequence of certain events which, in the worst case, performs the exhaustive search of error bursts, but in many cases the search may be significantly decreased by using the proposed heuristics. The proposed recursive decoding algorithm allows a guaranteed correction of any single error bursts within burst-correction capability of the code, and in many cases beyond the burst-correction capability. The complexity of this algorithm is significantly lower than that of a bit flipping algorithm if the parity-check matrix of the code is sparse enough. An alternative hybrid decoding algorithm is proposed utilizing the bit-flipping approach and showing the error probability and completion time comparable to the recursive algorithm, however, in this case the possibility of a guaranteed burst correction hardly can be proved. Practical relevance: The proposed decoding methods may be used in modern and perspective communication systems, allowing energy saving and increasing reliability of data transmission by better error performance and computational complexity.

Improved noisy gradient descent bit-flipping algorithm over Rayleigh fading channel

&lt;span&gt;Gradient descent bit flipping (GDBF) and its many variants have offered remarkable improvements over legacy, or modified, bit flipping decoding techniques in case of decoding low density parity check (LDPC) codes. GDBF method and its many variants, such as noisy gradient descent bit flipping (NGDBF) have been extensively studied and their performances have been assessed over multiple channels such as binary symmetric channel (BSC), binary erasure channel (BEC) and additive white Gaussian noise (AWGN) channel. However, performance of the said decoders in more realistic channels or channel conditions have not been equally studied. An improved noisy gradient descent bit flipping algorithm is proposed in this paper that optimally decodes LDPC encoded codewords over Rayleigh fading channel and under various fade rates. Comparing to NGDBF method, our proposed decoder provides substantial improvements in both error performance of the code, and in the number of iterations required to achieve the said error performance. It subsequently reduces the end-to-end latency in applications with low or ultra-low latency requirements.&lt;/span&gt;

Suspicion Distillation Gradient Descent Bit-Flipping Algorithm.

We propose a novel variant of the gradient descent bit-flipping (GDBF) algorithm for decoding low-density parity-check (LDPC) codes over the binary symmetric channel. The new bit-flipping rule is based on the reliability information passed from neighboring nodes in the corresponding Tanner graph. The name SuspicionDistillation reflects the main feature of the algorithm—that in every iteration, we assign a level of suspicion to each variable node about its current bit value. The level of suspicion of a variable node is used to decide whether the corresponding bit will be flipped. In addition, in each iteration, we determine the number of satisfied and unsatisfied checks that connect a suspicious node with other suspicious variable nodes. In this way, in the course of iteration, we “distill” such suspicious bits and flip them. The deterministic nature of the proposed algorithm results in a low-complexity implementation, as the bit-flipping rule can be obtained by modifying the original GDBF rule by using basic logic gates, and the modification is not applied in all decoding iterations. Furthermore, we present a more general framework based on deterministic re-initialization of the decoder input. The performance of the resulting algorithm is analyzed for the codes with various code lengths, and significant performance improvements are observed compared to the state-of-the-art hard-decision-decoding algorithms.

Iterative Hard-Decision Decoding Algorithms for Binary Reed-Muller Codes

In this paper, novel hard-decision iterative decoding algorithms for binary Reed-Muller (RM) codes are presented. First, two algorithms are devised based on the majority-logic decoding algorithm with reliability measures of the received sequence. The bit-flipping (BF) and the normalized bit-flipping (NBF) decoding algorithms are hard-decision decoding algorithms. According to the updated hard reliability measures, the BF and NBF algorithms flip one bit of the received hard-decision sequence at a time in each iteration. The NBF decoding algorithm performs better than the BF decoding algorithm by normalizing the reliability measures of the information bits. Moreover, the BF and NBF algorithms are modified to flip multiple bits in one iteration to reduce the average number of iterations. The modified decoding algorithms are called the multiple-bits-flipping (MBF) algorithm and the normalized multiple-bits-flipping (NMBF) algorithm, respectively. The proposed algorithms have low computational complexities and can converge rapidly after a small number of iterations. The simulation results show that the proposed hard-decision decoding algorithms outperform the conventional decoding algorithm.

A Low-Latency BF Decoding of LDPC Codes With Dynamic Thresholds

This letter proposes a high throughput bit-flipping (BF) algorithm for regular LDPC codes with dynamic thresholds. In the iterative decoding, the flipping threshold is dynamically updated according to the previous flipping results. Compared to the exiting hard-information-based BF algorithms, the proposed algorithm can get better decoding performance. At the same time, in order to accelerate the convergence speed, we limit the number of occurrences of high thresholds which effectively reduces the invalid decoding iterations. The proposed algorithm has better decoding performance and lower average number of iterations which is suitable for the flash storage systems with low latency and high throughput requirements.

타부 목록 확률적 순차 가변 임계값 경사 하강 비트 반전 알고리즘

본 논문은 저밀도 패리티 검사 (low-density parity-check, LDPC) 부호의 비트 반전 알고리즘(bit-flipping algorithm, BFA)의 부호 오류율 (Word Error Rate, WER) 및 복호 속도 개선에 관한 연구이다. 비트 반전 알고리즘은 비트의 신뢰도를 측정하는 측도인 반전 함수 (flipping function) 값의 임계값을 초과하는 비트를 반전시켜 오류를 정정하는 방식으로 동작한다. 본 논문에서는 반전 함수의 국소 최댓값을 이용해 반전 함수의 임계값을 매 반복마다 적응적으로 설정하여 반복 복호 횟수와 임계값을 찾는데 필요한 정렬 복잡도를 감소시키고, 복호 실패의 주 원인 중 하나인 trapping set 문제를 해결하기 위해 확률적으로 비트를 반전시켜 부호 오류율을 개선하였다.

On the modification of bit-flipping decoder of LDPC-codes

Introduction. In all types of digital communication, error control coding techniques are used. Many digital communication standards, such as Wi-Fi and 5G, use low density parity check (LDPC) codes. These codes are popular because they provide building encoders and decoders with low computational complexity. This work objective is to increase the error correcting capability of the well-known bit-flipping decoder (BF) of LDPC-codes. For this purpose, a modification of the decoder is built, which enables to dynamically control one of its main parameters whose choice affects significantly the quality of decoding. Materials and Methods. The well-known bit-flipping decoder of binary LDPC-codes is considered. This decoder has several parameters that are not rigidly bound with the code parameters. The dependence of the decoding quality on the selection of the output parameters of the bit-flipping decoder was investigated through simulation modeling. It is shown that the decoding results in this case are significantly affected by the input parameter of the decoder — threshold T. A modification of the BF-decoder of binary LDPC-codes has been developed, in which it is proposed to set the threshold dynamically during the execution of the algorithm depending on the error rate. A comparative analysis of the error- correcting capability of decoders is carried out by the simulation modeling method. Results. A lemma on the maximum value of the decoder threshold T is formulated and proved. Upper bounds for the number of operations are found for the original and modified decoders. A simulation model that implements a digital noise-immune communication channel has been built. In the model, the initial data is encoded with a given LDPC-code, then it is made noisy by additive uniformly distributed errors, and thereafter, it is decoded in turn by the bit-flipping algorithm with different threshold T parameters, as well as by a modified decoder. Based on the input and output data, the correction capacity of the decoders used is estimated. Experiments have shown that the error-correcting capability of the modified decoder in the range of the real error rate is higher than that of the original decoder, regardless of the selection of its parameters. Discussion and Conclusions. The lemma, proved in the paper, sets the upper bound on the threshold value in the original decoder, which simplifies its adjustment. The developed modification of the decoder has a better error- correcting capability compared to the original decoder. Nevertheless, the complexity of the modification is slightly increased compared to the original algorithm. It has been pointed out that the decoding quality of a modified decoder develops with a decrease in the number of cycles in the Tanner graph and an increase in the length of the code.

Low-complexity decoding of LDPC codes using reduced-set WBF-based algorithms

We propose a method to substantially reduce the computational complexity of iterative decoders of low-density parity-check (LDPC) codes which are based on the weighted bit-flipping (WBF) algorithm. In this method, the WBF-based decoders are modified so that the flipping function is calculated only over a reduced set of variable nodes. An explicit expression for the achieved complexity gain is provided and it is shown that for a code of block length N, the decoding complexity is reduced from O(N2) to O(N). Moreover, we derive an upper bound for the difference in the frame error rate of the reduced-set decoders and the original WBF-based decoders, and it is shown that the error performances of the two decoders are essentially the same.

Improved Belief Propagation Polar Decoders With Bit-Flipping Algorithms

Since the inherent serial nature of successive cancellation list (SCL) decoding results in a long latency, belief propagation (BP) decoding for polar codes has drawn attention for high-throughput applications. However, its error correction performance is inferior to that of SCL decoding. Therefore, the bit-flipping strategy has been recently applied to BP decoding, which can approach the SCL decoding performance through multiple additional decoding attempts. The original BP flip (BPF) decoding suffers from an inaccurate identification of erroneous bits by a fixed flip set (FS), which has been improved by the generalized BPF (GBPF) decoding. In this article, the GBPF decoding is extended to support multiple bits being flipped in one decoding attempt. In addition, for two types of decoding errors: detected errors and undetected errors, we propose two novel methods to more effectively identify erroneous bits. For detected errors, the concept of loop sets is defined and a loop-based identification method is introduced based on the study of error patterns of BP decoding. On the other hand, a method to generate a more accurate fixed FS is proposed for undetected errors, which considers the bit error distribution under BP decoding. Combining the two methods, the GBPF with merged sets (GBPF-MS) decoding can achieve the SCL-8 performance and outperforms the state-of-the-art BPF, BP list, and SC flip (SCF) decoding, for polar codes with length 1024 and information rate 1/2. Implemented by 40nm CMOS technology, the proposed GBPF-MS decoder with ten flips exhibits an average throughput of 4.19 Gbps at 2.5 dB, which is $1.6\times $ and $1.72\times $ faster than the state-of-the-art SCL-4 and SCF decoders, respectively.

Fine-Grained Bit-Flipping Decoding for LDPC Codes

This brief presents a novel class of hard-decision algorithms for decoding low density parity check codes. The new algorithms, named fine-grained bit-flipping (FBF) algorithms, employ a detailed classification of each bit, by introducing the XOR value of its estimated and received value as a subdividing criterion. The fine-grained classification allows the algorithms to strengthen the information utilization during each iteration. Simulation results show that the FBF algorithms can achieve up to 5 times better decoding performance than the state-of-the-art bit-flipping algorithms over the binary symmetric channel. Additionally, a well-optimized hardware architecture is developed for implementing FBF algorithms. Compared to other decoders, implementation results demonstrate that the FBF decoders achieve higher throughput and area efficiency.

Performance Study and Synthesis of the New LDPC Error Correcting Code Using the Bit-Flipping Algorithm

The discovery in 1993 of the turbo codes Berrou C., A. and P. Glavieux Thitimajshima at the International Conference of Communication Florida has revolutionized communication. This innovation made it possible to rediscovery the error correcting codes invented by Robert Gallager in 1963 and rediscovered by Mackay in 1995, currently called Low Density Parity Check (LDPC). This code is one of the error correction codes introduced by the transmission channel that have the fastest and most effective level of protection and correction of the information transmitted during the communication. This code has been almost generalized in communication standards such as satellites. The objective of our article is to minimize the number of iterations and in some cases completely remove the iteration produced by the LDPC code bit flipping algorithm. The result of this algorithm, if we take for example the LDPC code (n, k), the number of possible syndromes which we can find is 2k-1 and for each syndrome different from zero, we can do almost four iterations to correct the errors, which gives 4x(2k-1) iterations in totality. On the other hand, the proposed algorithm removes the iteration for k syndromes and reduces iterations for the rest of the cases from four to two iterations. This study of the new design gave more performance results and the results of the simulation below according to a hardware description language used in digital electronics using quartus software tools show the importance of this algorithm.

Gradient-descent decoding of one-step majority-logic decodable codes

In this paper, a new low-complexity gradient-descent based iterative majority-logic decoder (GD-MLGD) is proposed for decoding One-Step Majority-Logic Decodable (OSMLD) codes. We give a formulation of the decoding problem of binary OSMLD codes, as a maximization problem of a derivable objective function. The optimization problem is solved using a pseudo gradient-descent algorithm, which performs iteratively an update towards the optimal estimated codeword been transmitted, based on the first-order partial derivatives of each variable calculated in the previous iteration. The proposed decoding scheme achieves a fast convergence to an optimum codeword compared to other decoding techniques reviewed in this paper, at the cost of lower computational complexity. The quantized version (QGD-MLGD) is also proposed in order to further reduce the computational complexity. Simulation results show that the proposed decoding algorithms outperform all the existing majority-logic decoding schemes, and also various gradient-descent based bit-flipping algorithms, and performs nearly close to the belief propagation sum–product (BP-SP) decoding algorithm of LDPC codes, especially for high code lengths, providing an efficient trade-off between performance and decoding complexity. Moreover, the proposed quantized algorithm has shown to perform better than all the existing decoding techniques. The proposed decoding algorithms have shown to be suitable for ultra reliable, low latency and energy-constrained communication systems where both high performances and low-complexity are required.

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography

Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension.

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes

Low-complexity and high-performance low-density parity-check (LDPC) decoders are highly demanded in various modern communication and storage systems. In this paper, a novel hard-decision decoding algorithm, called tabu-list random-penalty gradient descent bit-flipping (TRGDBF) algorithm, is proposed. Compared to the state-of-the-art hard-decision algorithms, the TRGDBF algorithm has much better error-correction performance due to several algorithmic improvements. First, a random-penalty term is introduced to the inversion function to help the decoder escape from trapping sets, which are the main causes of the error-floor phenomenon. Second, a tabu-list is employed to improve the decoding efficiency. Numerical results show that the TRGDBF algorithm can achieve up to two orders of magnitude better error-correction performance than the probabilistic gradient descent bit-flipping (PGDBF) algorithm and reduce the average iteration count by about 15%. In addition, a well-optimized hardware architecture is developed to implement the TRGDBF algorithm. Algorithmic transformation and architecture optimization are well explored to reduce the hardware complexity and latency. Synthesis results show that the TRGDBF decoder can work at a higher frequency and offer a larger throughput than the PGDBF decoder.

Construction of 1-Bit Transmit-Signal Vectors for Downlink MU-MISO Systems With PSK Signaling

We consider a downlink multi-user multiple-input single-output system where the base station has a large number of antennas with cost-effective 1-b digital-to-analog converters. For this system, we first identify that assigning the zero-power to some transmit signals (in short, zero-power allocation) can yield a non-trivial symbol-error-rate performance gain by alleviating an error-floor problem. Likewise the related works on 1-b precoding, finding an optimal transmit-signal vector (encompassing precoding and zero-power allocation) requires an exhaustive search due to its combinatorial nature. Motivated by this, we propose a low-complexity two-stage algorithm to construct such transmit-signal vector directly. In the first stage, we derive a feasible transmit-signal vector via iterative-soft-thresholding algorithm whose output ensures that each user's noiseless observation belong to a desired region (called decision region). In the second stage, a bit-flipping algorithm is performed to refine the feasible vector so that each user's received signal is more robust to additive Gaussian noises. Simulation results demonstrate that the proposed method can yield a more elegant performance-complexity tradeoff than the existing 1-b precoding methods.

High‐throughput Bit Flipping decoder for structured LDPC codes

Low-density parity-check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high-throughput parallel bit-flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite-geometry LDPC (FG-LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG-LDPC codes, respectively. Compared to the state-of-the-art design, the proposed designs offer 4 . 5 times higher normalised throughput.