Bipolar LSIs Research Articles

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS, MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-/spl mu/m CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160/spl times/114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-/spl mu/m CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-/spl Omega/ strip lines, high-speed signal lines, and 33 power supply layers formed using 50-/spl mu/m thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80/spl times/120/spl times/20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection.

Advanced process device technology for 0.3- mu m high-performance bipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3- mu m bipolar LSIs. Fabricated 0.5- mu m U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 mu m/sup 2/, and they have an isolation width of 2.0 mu m, a minimum emitter width of 0.2 mu m, a maximum cutoff frequency (f/sub T/) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3- mu m bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f/sub T/ and base resistance is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Structure of outside emitter silicon bipolar transistor (OSET) for high‐speed LSI

AbstractTransistor structures suitable for high‐speed bipolar LSIs have been examined and OSET (outside emitter technology) transistors which enable an emitter region more than three times larger for the same base area are proposed. The feature of this transistor is the structure where the base contact region is placed in the center and a ring‐shaped emitter region is formed around it. As a result, the placement of the base and emitter regions is reversed compared to the conventional structure.With the OSET transistor with a ring‐shaped emitter region formed by a self‐aligned technology as a basis, a simple type with a simplified fabrication process, a ringed‐collector type with a ring‐shaped collector electrode outside the emitter to reduce the collector resistance and the area, and a central‐collector type which has a minimum active area have been examined.The central‐collector type transistor enables an emitter area of 2.6 μm2 in the device area of 2 × 2 μm2, and the emitter occupies an extremely high portion of the device region. The OSET transistor that enables a dramatic reduction of parasitic capacitances (which occupy a large portion of the LSI delay time) with device scaling is considered suitable for ultrahigh‐speed LSIs.

SATURN: Device technology for high‐speed bipolar LSIs

AbstractA new self‐alignment process technology SATURN (self alignment technology utilizing reserved nitride) has been developed in which the selective oxidation of polysilicon and the nitride films in this oxidation process are used for a number of objectives with a view to improve the operating speed of the bipolar devices. This method is characterized by the control of the emitter stripe width by the side wall spacer film thickness and the control of the distance between the emitter and the external base by the selective oxide film thickness are carried out independently. A process of optimization based on the forementioned control was carried out so that the small transistor with an emitter stripe width of 0.5 μm and a distance of 0.35 μm between the emitter contact and the base contact was realized. This resulted in a current gain of 66 and a cutoff frequency of 12 GHz. Further, this transistor was applied in the ECL circuit which resulted in the performance with the minimum propagation delay time of 88 ps in an inverter gate and the maximum dividing frequency of 3.5 GHz in a 1/8 divider.

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

SDX: a novel self-aligned technique and its application to high-speed bipolar LSIs

A novel polysilicon selective-deposition method named selective deposition by exdiffusion (SDX) and a self-aligned bipolar LSI process using the SDX process are presented. The SDX process makes it possible to selectively form polysilicon patterns on silicon oxide patterns but not on silicon nitride patterns, where these patterns are formed on a silicon substrate surface. Bipolar transistor self-alignment between the isolation pattern and the entire transistor active region can be achieved in a 0.85- mu m silicon island by the SDX process. A transistor with a 12-GHz cutoff frequency, an LCML gate with a propagation delay time of 59 ps/gate, and a 1-kb ECL (emitter-coupled logic) memory with an access time of 0.95 ns have been achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Generalized Manhattan path algorithm with applications

The author presents an efficient algorithm for finding a route interconnecting two terminals of arbitrary polygonal shape in two layers. The main feature of the router to be distinguished from the existing grid-free routers is that it can handle large vias. The author has also considered the extension to multi-terminal nets and demonstrate a native algorithm which repeats the same path finding process for each constituent terminal. Careful considerations may lead to a more efficient way such that three regions (horizontal and vertical routable regions and via acceptable region) are not reconstructed each time but updated only around the path obtained. In order to do that a data structure has been devised which can implement insertions and deletions of line segments each in O(log n) time. Based on the proposed algorithm it is possible to solve a practical problem which is concerned with a layout design of bipolar LSIs. In this case the purpose is to find an orthogonal wiring route of predetermined width between pairs of terminals avoiding polygonal obstacles in two layers. >

Perspective on BiCMOS VLSIs

A high-performance BiCMOS technology (Hi-BiCMOS) and its applications to VLSIs are described. By combining bipolar and CMOS devices in unit circuits of VLSIs, Hi-BiCMOS provides both speed performance competitive with bipolar LSIs and integration density close to that of CMOS LSIs. Hi-BiCMOS technology has been successfully used for static RAMs, dynamic RAMs, and gate arrays. The effectiveness of its applications to some types of processors has also been examined by evaluating test chips.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hi‐bicmos 32‐bit execution unit

AbstractThe applicability of the Hi‐BiCMOS (High Performance Bipolar CMOS) technology to the 32‐bit execution unit has been researched to improve the function and speed of such processors as minicomputers CPUs. The HiBiCMOS technology enables MOS devices with performance comparable to pure CMOS LSIs and bipolar devices with performance comparable to pure bipolar LSIs to be combined on the same substrate. Device integrations comparable to CMOS LSIs have been achieved by the utilization of macrocells composed mainly of MOS circuits. Attempts have been made to speed‐up the macrocells by adding Hi‐BiCMOS circuits.In this paper, the feedback‐type smallamplitude precharge circuit is proposed and fabricated. This circuit affords precise bus voltage. Also, the carry propagation circuit that uses the bipolar sense amplifier to achieve the machine cycle of 25 ns is proposed. Consequently it is confirmed that the precharge circuit operates two times faster and the carry propagation circuit 3.3 times faster than pure CMOS circuits. Thus, one of the promising candidates for the ultrahigh‐speed one‐chip processors is shown.

Polysilicon self-aligned technology — a new approach for bipolar LSIs: K. Okada, K. Aomura, T. Nakamura and H. Shiba NEC Res. Dev. (Jpn), 56, 170 (January 1980)

Polysilicon self-aligned technology — a new approach for bipolar LSIs: K. Okada, K. Aomura, T. Nakamura and H. Shiba NEC Res. Dev. (Jpn), 56, 170 (January 1980)

Polysilicon self-aligned technology—A new approach for bipolar LSIs : Kenji Okada, Kunio Aomura, Toshio Nakamura and Hiroshi Shiba. NEC Res. Dev. (Jpn). 56, 170 (January 1980)

Polysilicon self-aligned technology—A new approach for bipolar LSIs : Kenji Okada, Kunio Aomura, Toshio Nakamura and Hiroshi Shiba. NEC Res. Dev. (Jpn). 56, 170 (January 1980)