Abstract
A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3- mu m bipolar LSIs. Fabricated 0.5- mu m U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 mu m/sup 2/, and they have an isolation width of 2.0 mu m, a minimum emitter width of 0.2 mu m, a maximum cutoff frequency (f/sub T/) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3- mu m bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f/sub T/ and base resistance is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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