Bipolar Differential Pair Research Articles

Analysis of Electrothermal Effects in Bipolar Differential Pairs

An extensive experimental and theoretical analysis of bipolar differential pairs subject to radical electrothermal feedback is presented. Measurements demonstrate that considerable thermally-induced degradation of circuit characteristics may occur, eventually turning into the full disappearance of a linear region, which is replaced by a hysteresis behavior under voltage-controlled conditions. An analytical model is derived for a simple yet reliable prediction of the distortion of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I$</tex></formula> – <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V$</tex></formula> curves. A more elaborated circuit approach is employed to accurately quantify the concurrent destabilizing action of electrothermal and impact ionization effects, as well as to evaluate the impact of layout asymmetries and examine the beneficial influence of emitter degeneration resistors. Simulation results are found to compare favorably with experiments performed on silicon-on-glass test structures with various layouts and isolation schemes, from which the benefits of thermally coupling the two devices become evident.

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$m Direct Digital Synthesizer

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 mum technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An Analysis of $1/f^{2}$ Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators)

This work presents an analysis of phase noise in the 1/f2 region displayed by both single-ended and differential bipolar Colpitts oscillators. Very accurate and rigorous symbolic phase noise expressions are derived, enabling a deeper insight into the major mechanisms of phase noise generation, and providing new tools for design optimization. Phase noise expressions for the cross-coupled differential-pair LC-tank oscillator are derived as well. The theoretical analysis is validated on a 3 GHz differential bipolar Colpitts VCO implemented in a 0.35 mum SiGe process. Measurements show a phase noise of -123 dBc/Hz or less at 1MHz offset frequency from the 2.8-3.1 GHz carrier, for a phase noise figure-of-merit of at least 183 dBc/Hz across the tuning range. A very good agreement between theory, numerical simulations, and measurements is observed

Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers

An even-harmonic mixer using a bipolar differential pair (bipolar harmonic mixer;BHMIX) is theoretically analyzed from the direct conversion point of view; i.e, conversion gain, third-order input intercept point (IIP3), self-mixing induced dc offset level, and second-order input intercept point (IIP2). Also, noise are analyzed based on nonlinear large-signal model, and numerical results are given. Noises are treated as cyclostationary noises, thus all the folding effects are taken into account. Factors determining IIP3, IIP2, dc offset, and noise are identified and estimation procedures for these characteristics are obtained. For example, design guidelines for the optimal noise performance are given. Measured results support all the analysis results, and they are very useful in the practical BHMIX design.

Jitter in ring oscillators

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

A 10-bit 100 MSamples/s BiCMOS D/A Converter

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8\mu m BiCMOS process and is designed to operate at a sampling rate of 100i>MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of approximately 650m W. The area of the chip-core is 2.2mm\times 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f_g\approx 0.1\cdot f_s(f_s = 100\hbox{\it MSamples}/s) the measured SFDR is 50dB, and at f_g\approx 0.3\cdot f_s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140i>MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.

Generation of a neuron transfer function and its derivatives

A new simple circuit is presented that can be used to realise both a neuron transfer function and its approximate derivative, making it possible to use the same hardware in both learning and recall phase of the ANN. The mode of operation is digitally controlled. A CMOS differential pair has been used for realising the neuron transfer function, but a bipolar differential pair could be used equally well.

Bipolar differential pair DC transfer characteristics

Starting from the partition function the energy of a system which leads to the derivation of collector currents in the circuit is determined. From the currents the large-signal transfer characteristics of the emitter-coupled pair are obtained. This new technique provides an insight into the statistical nature of charge carriers in a system.

BiCMOS DCVSL gate

A BiCMOS differential cascode voltage switch logic (DCVSL) gate is presented. The circuit consists of a CMOS differential logic circuit and a bipolar differential sense pair. The result is a high speed CMOS to ECL conversion circuit with relatively high logic density. Simulation results of a test circuit are presented and indicate that this logic gate is competitive with ECL in terms of speed and with CMOS in terms of integration density.

Fully differential operational amplifiers using CMOS compatible ateral bipolar transistors with improved common-mode regulation

A new bias circuit for a CMOS compatible lateral bipolar transistor differential pair is presented. The circuit compensates for all process and bias dependent variations of the lateral collector current to emitter current ratio α. Experimental results show that its application to a fully differential amplifier improves the precision of the common-mode output voltage regulation by at least an order of magnitude.

An 8-bit 200-MHz BiCMOS comparator

The design of a fully differential BiCMOS comparator suitable for application in data conversion, instrumentation, and communication systems operating at video frequencies and above is discussed. By exploiting the advantages presented by the integration of both bipolar and CMOS devices within the same technology, the comparator dissipates less power than conventional bipolar designs without sacrificing operating speed. The comparator includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. This stage dissipates no static power and, because the amplification is provided by a bipolar differential pair, no offset cancellation is needed to achieve 8-b precision. Furthermore, the need for preamplification and the attendant power-delay penalty associated with preamplifier overdrive recovery are avoided. An experimental version of the comparator, consisting of the BiCMOS regenerative input stage followed by a current-switched latch, has been integrated in a 0.8- mu m BiCMOS technology with an area of 140*75 mu m. This circuit performs comparisons to a precision of 8 b at rates up to 200 MHz. The entire circuit dissipates only 1.6 mW at the maximum clock rate while operating from a single 5-V supply. >

Automatic gain control by differential pair current splitting

A bipolar differential pair used as a current splitter is applied in the amplifier automatic gain control (AGC) circuit. The output voltage of the intermediate amplifier supplies current (via a resistor) to the point of emitter coupling of the differential pair. The current splitting is controlled by the base voltages of the pair. One collector output of this pair is used to provide additional voltage controlled feedback in the intermediate amplifier, another output provides the voltage controlled signal transfer to the output amplifier. The proposed method is applied to low-voltage power supply bandpass amplifier circuit. The gain control of 40 dB with − 47 dB total harmonic distortions (THD) in the total gain control range was achieved with a power supply of 3-75 V.

Gain and bandwidth characteristics of a variable-gain, actively neutralized bipolar differential pair

The gain and bandwidth characteristics of a neutralized bipolar differential pair are analyzed, and results are compared with measurements performed on three integrated circuit test cells. A simple two-port model of the neutralized pair is derived through application of signal flow and dominant pole theories. This model is fully capable of predicting gain and 3-dB bandwidth as a function of a bias current applied to control gain magnitude.