A 10-bit 100 MSamples/s BiCMOS D/A Converter

Abstract

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8\mu m BiCMOS process and is designed to operate at a sampling rate of 100i>MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of approximately 650m W. The area of the chip-core is 2.2mm\times 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f_g\approx 0.1\cdot f_s(f_s = 100\hbox{\it MSamples}/s) the measured SFDR is 50dB, and at f_g\approx 0.3\cdot f_s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140i>MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.