Binary Successive Approximation Research Articles

A New Successive Time Balancing Time-to-Digital Conversion Method.

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing.

Systematization and Comparison of the Binary Successive Approximation Variants.

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants.

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 μW and 10.4 μW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 × 16 pixel matrix.

Unit commitment considering dual-mode combined heat and power generating units using integrated optimization technique

In this work, we have undertaken a dual-mode combined heat and power unit commitment model to address the optimum generation scheduling of the committed unit. The model formulation includes the backpressure and an extraction mode of cogeneration unit, which is having a diverse feasible operating region of operation. In backpressure mode, the energy generated from the combined heat and power unit depends on a fixed ratio of power and heat, while in extraction mode, this ratio is relatively relaxed that provides system flexibility as compared to other. Owing to the dynamic features of different generating units as well as combination of binary and continuous decision variables, the problem becomes mixed-integer nondeterministic polynomialhard optimization problem, hence an integrated optimization technique has been applied. The integrated optimization technique is a combination of binary successive approximation technique and civilized swarm optimization technique. The binary successive approximation as a local search technique is used to update the unit status, iteratively and global search technique ‘civilized swarm optimization’ are applied to search optimal generation schedule from the committed units. In order to measure the impact of a dual-mode combined heat and power unit on optimum generation scheduling and system flexibility, four test systems have been undertaken. It has been observed from results that total operating cost of the system during extraction mode of combined heat and power unit is less as compared to backpressure mode. It is also evident from the results, that system provides diverse flexibility in terms of power and heat capability, during the extraction and backpressure mode of operation.

Design of Digital IIR Filter with Conflicting Objectives Using Hybrid Predator–Prey Optimization

The design of digital IIR filter as a single-objective optimization problem using evolutionary algorithms has gained much attention in the previous years. In this paper, the design of filter is treated as a multi-objective problem by simultaneously minimizing the magnitude response error, linear phase response error and optimal order within the stability constraints. The global search technique, predator–prey optimization (PPO), has been applied to design the digital IIR filter. The global search technique has been hybridized with binary successive approximation (BSA)-based evolutionary search method for exploring the search space locally. The relative performance of PPO and hybrid PPO has been evaluated by applying these techniques to standard mathematical test functions. The above-proposed hybrid search technique has been applied to achieve the solution for multi-parameter and multi-objective optimization problem of low-pass (LP), high-pass (HP), band-pass (BP) and band-stop (BS) digital IIR filter design. The results obtained from the proposed technique are compared with the results of other algorithms applied by other researchers for the design of digital IIR filter.

Hybrid heuristic search method for design of digital IIR filter with conflicting objectives

The design of digital IIR filter design by using evolutionary algorithms has gained much attention in the previous years. Most of the researchers treated the design problem as a single objective optimization problem and applied the techniques for minimizing the magnitude response error. In this paper the design of filter is treated as a multi-objective problem by simultaneously minimizing the magnitude response error, linear phase response error and optimal order along with meeting the stability criterion. A hybrid heuristic search technique having differential evolution (DE) method as a global search technique and binary successive approximation based evolutionary search method as a local search technique has been proposed. Based on mean value of population, new mutation strategies have been proposed. The above proposed hybrid heuristic search technique has been applied effectively to solve the multi-parameter and multi-objective optimization problem of low-pass, high-pass, band-pass and band-stop digital IIR filter design. The obtained results reveal that the proposed technique with new proposed mutation strategies performs better than the already existing mutation strategies of DE and other algorithms applied by other researchers for the design of digital IIR filter.

A new greedy search method for the design of digital IIR filter

A new greedy search method is applied in this paper to design the optimal digital infinite impulse response (IIR) filter. The greedy search method is based on binary successive approximation (BSA) and evolutionary search (ES). The suggested greedy search method optimizes the magnitude response and the phase response simultaneously and also finds the lowest order of the filter. The order of the filter is controlled by a control gene whose value is also optimized along with the filter coefficients to obtain optimum order of designed IIR filter. The stability constraints of IIR filter are taken care of during the design procedure. To determine the trade-off relationship between conflicting objectives in the non-inferior domain, the weighting method is exploited. The proposed approach is effectively applied to solve the multiobjective optimization problems of designing the digital low-pass (LP), high-pass (HP), bandpass (BP), and bandstop (BS) filters. It has been demonstrated that this technique not only fulfills all types of filter performance requirements, but also the lowest order of the filter can be found. The computational experiments show that the proposed approach gives better digital IIR filters than the existing evolutionary algorithm (EA) based methods.

Design of Digital IIR Filter with Conflicting Objectives Using Hybrid Gravitational Search Algorithm

In the recent years, the digital IIR filter design as a single objective optimization problem using evolutionary algorithms has gained much attention. In this paper, the digital IIR filter design is treated as a multiobjective problem by minimizing the magnitude response error, linear phase response error and optimal order simultaneously along with meeting the stability criterion. Hybrid gravitational search algorithm (HGSA) has been applied to design the digital IIR filter. GSA technique is hybridized with binary successive approximation (BSA) based evolutionary search method for exploring the search space locally. The relative performance of GSA and hybrid GSA has been evaluated by applying these techniques to standard mathematical test functions. The above proposed hybrid search techniques have been applied effectively to solve the multiparameter and multiobjective optimization problem of low-pass (LP), high-pass (HP), band-pass (BP), and band-stop (BS) digital IIR filter design. The obtained results reveal that the proposed technique performs better than other algorithms applied by other researchers for the design of digital IIR filter with conflicting objectives.

A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , it achieves a peak SNDR of 31.5 dB at 1GS/s sampling rate and has a total power consumption of 6.7 mW.

Digital error correction technique for binary decision successive approximation ADCs

A digital error correction technique with negligible hardware overhead is proposed for binary successive approximation ADCs. A redundant decision phase is inserted between the normal SAR operations, and the coarse decision error caused by incomplete DAC settling is corrected by a digital code addition. The relaxed DAC settling requirement for coarse decision increases the conversion speed.