Binary Rate Multiplier Research Articles

Realization of a Digital Differential Analyzer Using CPLDs

The objective is to design and fabricate a wire programmable discrete version of an analog computer known as the digital differential analyzer (DDA) using the binary rate multiplier (BRM) principle without using analog components like operational amplifiers. The bandwidth of the elements can be more than 50kHz. The BRM enables arithmetic-free signal processing. Programming a DDA based on the BRM principle is very similar to the programming of an analog computer due to the structural similarity. The DDA described in this paper uses two wires each at the input and the output ports. One wire is used for carrying the magnitude of the signal in the pulse-rate form and the other wire for the sign of the signal. The paper aims at simulating and synthesizing various modules of a stand-alone-DDA and downloading the synthesized modules on to complex programmable logic devices (CPLDs). Interconnecting various modules in the CPLD can solve differential equations. The results obtained in real time were verified by simulation using (i) ModelSim, (ii) Simulink and (iii) analytical solution of equivalent Z-domain blocks.

REALIZATION OF A DIGITAL DIFFERENTIAL ANALYZER USING CPLDs

The objective is to design and fabricate a wire programmable discreteversion of an analog computer known as the digital differentialanalyzer (DDA) using the binary rate multiplier (BRM) principlewithout using analog components like operational amplifiers.

Temperature control using integer-cycle binary rate modulation of the AC mains

This paper describes a unique and novel method of maintaining the temperature of an oven when the power is dispatched in an integral AC cycle pulse modulated manner. The pulse rate is performed by a microprocessor implemented binary rate multiplier, allowing for minimal ripple in the oven temperature. Conditions for stability of the overall system are examined and the time response of the system is estimated from a model of the plant, controller and binary rate dispatch algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Binary rate modulation, its application and stability in control systems

This paper describes a set of piecewise constant waveforms which, when used as the method of dispatch of power to a first-order system, offers distinct advantages over other piecewise constant signal methods. The waveforms are similar to those which are produced by binary rate multipliers and the technique is called ‘Binary Rate Modulation’. The stability of the resulting discrete closed loop system is investigated using a circle criterion adaptation, applied to a multiple nonlinearity, with a multiple pulse output in each nonlinearity and by a proposed ultimate linear technique. The gains for asymptotic stability and limit cycling are found from the techniques. Results in accordance with the predicted values are obtained from observed system responses. The two stability techniques can be easily applied to systems using pulse width or pulse frequency modulation output drives to first-order systems.

Correspondence between Walsh functions and binary rate multiplier pulse trains

Abstract A direct correspondence is shown to exist between even Walsh functions and binary rate multiplier (BRM) output trains. It can be concluded from this correspondence that Walsh functions can be conceived of as derived from the BRM output trains by frequency division by two.

Maximum pulse-position and counting errors of binary rate multipliers

The paper examines systematically the error properties of binary rate multipliers (BRMs). Simple close-form expressions for the maximum pulse-position and counting errors are given for a number of timing variants. It is seen from the paper that the so far reported estimates of the errors, valid for a certain timing variant, are too optimistic in general. A brief discussion of the effect on the errors of a frequency divider applied to the output of the BRM is also provided.

A novel digital power-factor meter design

This paper describes a novel design for a digital power-factor (PF) meter. The design is based on a new digital processor that gives an output frequency proportional to its input voltage, as well as a digital output inversely proportional to the input voltage. The output frequency is made directly proportional to the product of the peak voltage and the power factor V m cos ⊘, while the digital output is inversely proportional to the peak voltage V m . The digital and frequency outputs are applied to a binary rate multiplier (BRM). The BRM frequency output is summed over a specified period of time to provide PF information.

Calculation and display of the rate/pressure product during anaesthesia using binary rate multipliers.

Calculation and display of the rate/pressure product during anaesthesia using binary rate multipliers.

Linear equivalence of certain BRM shift-register sequences

A theorem given by Albert is used to show that if a shift register of length m is used to clock another shift register of length n through a binary rate-multiplier, then it can easily be arranged that the output has a linear equivalence of (2m _ 1)n and a period of (2m _ 1)(2n _ 1).

A versatile CMOS rate multiplier/variable divider

A versatile integrated circuit that delivers an optimally spaced output signal is presented. The paper includes a comparison of the commonly used rate-multiplication scheme and the accumulator rate-multiplier principle. It is shown that this principle always delivers the best possible digital approximation of a regular signal, but it is inherently slower. The design considerations for speed improvement are described, together with a scheme that leads to the special feature of a programmable denominator. In this case, the circuit can be used as, for example, a binary rate multiplier, BCD rate multiplier, and variable divider, etc. Cascading possibilities are shown, and some application areas are given. The circuit is ideally suited for use as a microprocessor compatible peripheral circuit in digital control systems.

Design of computing circuits for pulse frequency coded signals

This paper describes the realization of circuits which operate on signals represented in pulse.rate form. For this, one needs a series of digital circuits such as the binary rate multiplier (BRM), accumulator rate multiplier (ARM), counters, frequency divider etc. Two channels have boon used to represented the information, one with a logical level indicating the sign and the other with the frequency of the pulse train indicating the absolute value. Finally some applications of the developed circuits are shown.

A Digital Power-Factor Meter Design Based on Binary Rate Multiplication Techniques

This paper relates to the field of developing an electronic power-factor (PF) meter to replace the conventional electrodynamic type. The design is based on voltage to frequency conversion and binary rate multiplication techniques. For the first half measuring period, a signal proportional to the peak voltage Vm is applied to control the switching threshold level of the comparator of the voltage to frequency converter (VFC), while the input of the VFC is kept at suitable constant level, thus producing an output frequency inversely porportional to Vm, which is counted and applied as an input data to a binary rate multiplier (BRM). For the second half measuring period, a signal proportional to the product of the peak voltage and the power factor Vm cos(?), is applied to the VFC, while the threshold level of the comparator is kept constant. The VFC frequency output is then directly proportional to Vm cos(?). This is made available through gating network to the BRM frequency input. The BRM frequency output is summed over a specified period of time to provide PF information.

Fast digital vector- and circle generator with binary rate

Digital graphic generators can be used as interfaces to different graphic output devices such as plotters, vector and raster-scan displays. The principle of digital vector and circle generation with binary rate multipliers (BRM) is represented. There is given a formula which describes the discrete approximation of the ideal BRM function.

Determination of binary rate multipliers error utilizing a digital computer programme

Hsi-Zeng has given a method for evaluation of the maximum error of a binary rate multiplier. The present paper extends the method and outlines some of the formulae that are different to Hsi-Zeng's.

Digital NMR frequency to magnetic field converter

A simple inexpensive circuit is described which digitally converts the frequency of an NMR gaussmeter to gauss. The circuit uses synchronous binary rate multipliers and performs the conversion immediately and with arbitrarily high precision.

Shift Register Binary Rate Multipliers

Novel implementations of a binary rate multiplier (BRM) circuit are described. These BRM's, which use the input data word to load patterns into shift registers, are capable of working at higher speed than a conventional circuit, and should be more suitable for silicon integration. Long input data words can be accommodated with a long shift register or by interconnecting several short registers.

High Accuracy and Fast Response Digital Speed Measurement for Control of Industrial Motor Drives

This paper concerns digital speed control for high performance industrial drives (paper machines, rolling mills etc.) based on a novel principle for frequency measurement.In sections 1-2 the principle and theory for digital measurement of angular velocity by means of a low resolution pulse transmitter and the new frequency-to-digital convertor is presented. This system gives high measurement accuracy and resolution combined with short measuring time within a wide speed range at a low ripple content. Further, in section 3 it is shown how this F/D convertor, consisting of a binary rate multiplier, an up/down counter and a register can be built with a few digital integrated circuits.The next section describes the design of the speed control system for a thyristor controlled DC motor drive based on the new F/D convertor. Significantly better steady state accuracy and linearity (better than 0.01 %) compared with present analogue systems has been achieved. The dynamic control performance is also better than that of most analogue systems available (response time better than 30 ms for a 100 kW drive). These characteristics are documented by experimental performance curves.In the last section, two industrial applications of such drives are described - one for a paper machine and one for a wire rod mill. In both cases microprocessor-based program-controlled electronics is used for digital overriding (higher level) control.

Matrix Representation of the Multiplying Properties of Binary Rate Multipliers

An exact representation of the multiplying property of a binary rate multiplier (BRM) is derived. The equations are in a simple matrix form with a common multiplier matrix, the order and elements of which are easily predicted for BRM's of any given bit magnitude. Equations are developed for particular input constraints and may be combined when more than one input constraint condition exists. The equations are of a form which is particularly useful in the analysis of digital feedback systems using BRM's.

An automatic dead time corrector

An all ICs NIM standard module Dead Time Corrector described here is for handling large random rates. The circuit employs a binary rate multiplier. Circuit diagram, experimental results and testing procedures are described. The unit allows selection of dead time 1.16, 2.32, 5.8 and 11.6 μs.

A study of an output interface for a digital stochastic computer

A theoretical and experimental investigation of adaptive digital elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics. The experimental results are shown to be in close agreement with the various theoretical predictions.