Abstract
This paper describes a novel design for a digital power-factor (PF) meter. The design is based on a new digital processor that gives an output frequency proportional to its input voltage, as well as a digital output inversely proportional to the input voltage. The output frequency is made directly proportional to the product of the peak voltage and the power factor V m cos ⊘, while the digital output is inversely proportional to the peak voltage V m . The digital and frequency outputs are applied to a binary rate multiplier (BRM). The BRM frequency output is summed over a specified period of time to provide PF information.
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