A Digital Power-Factor Meter Design Based on Binary Rate Multiplication Techniques

Abstract

This paper relates to the field of developing an electronic power-factor (PF) meter to replace the conventional electrodynamic type. The design is based on voltage to frequency conversion and binary rate multiplication techniques. For the first half measuring period, a signal proportional to the peak voltage Vm is applied to control the switching threshold level of the comparator of the voltage to frequency converter (VFC), while the input of the VFC is kept at suitable constant level, thus producing an output frequency inversely porportional to Vm, which is counted and applied as an input data to a binary rate multiplier (BRM). For the second half measuring period, a signal proportional to the product of the peak voltage and the power factor Vm cos(?), is applied to the VFC, while the threshold level of the comparator is kept constant. The VFC frequency output is then directly proportional to Vm cos(?). This is made available through gating network to the BRM frequency input. The BRM frequency output is summed over a specified period of time to provide PF information.