Binary Motion Estimation Research Articles

개선된 이진 블록 매칭 방법을 사용한 제한된 1비트 변환 알고리듬 기반 움직임 추정

In this paper, Enhanced binary block matching method for Constrained one-bit transform (C1BT) based motion estimation is proposed. Binary motion estimation exploits the Number of non-matched points (NNMP) as a block matching criterion instead of the Sum of Absolute Differences (SAD) for low complex motion estimation. The motion estimation using SAD could use the smaller block for more accurate motion estimation. In this paper the enhanced binary block matching method using smaller motion estimation block for C1BT is proposed to the more accurate binary matching. Experimental results shows that the proposed algorithm has better Peak Signal to Noise Ration PSNR) results compared with conventional binary transform algorithms. Keyword : Motion estimation, Block matching algorithm, One-bit transform, Constrained one-bit transform, Binary block

A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture

Higher quality video encoding is only one of many requirements in an industry increasingly interested in lower power consumption, upgradable standards flexibility, and lower cost. To date, meeting all needs at the same time has been unachievable, limited by inefficiencies in underlying silicon architectures and traditional programming methodologies. Legacy processing solutions using arrays of field programmable gate arrays (FPGAs), digital signal processors (DSPs), general purpose processors (GPPs), or inflexible application specific integrated circuits (ASICs) have forced designers to make feature set tradeoffs and solutions that do not scale well with increasing pixel rates. A new approach using a dataflow programming methodology and a massively parallel processor array introduces a step in improvement in meeting tomorrow's equipment requirement with respect to computationally intensive algorithms such as H.264 Hi10P, Level 4.1 or greater. This development flow allows for (1) rapid deployment, (2) software-defined implementation that is upgradable for new features or algorithm enhancements, and (3) high-quality/low power video encoding at the point of capture. We present two key components of an H.264 encoder—Context Adaptive Binary Arithmetic Coding (CABAC) and motion estimation—and demonstrate the application of the dataflow methodology on a massively parallel processor.

웨이블릿 변환을 이용한 보완된 이진 블록 정합 움직임 예측 알고리듬

영상 압축은 멀티미디어 전송에 있어 핵심적인 기술이다. 동영상 압축 기술 중 움직임 예측부는 전체 동영상 압축 부호화에서 가장 복잡한 부분으로, 멀티미디어의 실시간 전송을 위하여 고속 알고리듬이 필요한 부분이다. 본 논문은 기존의 고속 움직임 예측 알고리듬의 하나인 이진 블록 정합 움직임 예측 알고리듬을 개선하여 더욱 정확한 움직임 벡터를 찾는 방법을 제안한다. 제안하는 알고리듬은 웨이블릿 변환 후 고주파 대역의 정보값을 이용해 움직임 벡터를 찾음으로써 기존의 알고리듬을 개선한다. 제안하는 알고리듬은 기존의 알고리듬의 화질을 향상시킨다. Video Compression is the key technology for the transmission of multi-media data. Because the Motion Estimation is the most complex module in the video compression, fast motion estimation algorithm is essential for the real-time application. In this paper, we propose an enhanced binary motion estimation algorithm based on the wavelet transform. Proposed algorithm improve the quality of coded video.

Two-bit transform based block motion estimation using second derivatives

Binary motion estimation algorithms reduce the computational complexity of motion estimation, but, sometimes generate an inaccurate motion vector. This paper proposes a novel two-bit representation, called twobit transform-second derivatives (2BT-SD) which improves the efficiency of image binarization and the accuracy of motion estimation by making use of the positive and negative second derivatives independently in the derivation of the second bit plane. The second derivatives are also used to detect flat or background regions, avoiding expensive motion vector search operations for macroblocks in these areas, and deriving the motion vectors by prediction from neighboring blocks. In applying the proposed 2BT-SD in the H.264/AVC standard, a further reduction of motion estimation complexity with a minor accuracy reduction is achieved by using 2BT-SD representation for secondary motion estimation while using the full resolution representation for the primary motion estimation. A hardware cost analysis shows that about 209 K gates of hardware logics and 2.7 K bytes of memory are reduced by 2BT-SD for motion estimation of 1280times720 size videos when compared with the full resolution motion estimation. Experiments show that the proposed 2BT-SD achieves better motion estimation accuracy than other binary motion estimations and provides faster processing time in flat or background regions with an acceptable bit-rate increase.

A Low-Power and Bandwidth-Efficient Motion Estimation IP Core Design Using Binary Search

A new architecture design for motion estimation using binary matching criterion is proposed to achieve low power and bus bandwidth efficiency. Low power and high bus bandwidth efficiency are the two key issues for portable video applications. To address such issues, we first study an efficient algorithm called all binary motion estimation (ABME), and analyze its architecture issues in operational flow and bus access. Then, we propose an architecture for ABME with four new features: (1) macroblock level pre-processing; (2) efficient binary pyramid search structure; (3) parallel processing of 8 x 8 and 16 x 16 block searches; (4) parallel processing of bi-directional search. Such architecture leads to a superior performance in bus access, speed, and power. Our experiments show that the power consumption is as low as 763 mu W for IPPPP CIF 30 frames/s and 896 muW for IPBPB CIF 30 frames/s. The bus bandwidth savings are 54.3% for P-frame search and 67.1% for B-frame search.

An all binary sub-pixel motion estimation approach and its hardware architecture

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices.

VLSI design for MPEG-4 shape coding using a contour-based binary motion estimation algorithm

An efficient architecture with the fast algorithm for MPEG-4 shape coding is proposed. The authors apply the fast shape coding algorithm, with contour-based binary motion estimation (CBBME), which is based on the properties of a boundary mask. By using the block-matching motion estimation and the extended approach on centre-biased motion vector distribution with shrinking of the search range, a large number of search points in BME can be skipped. Based on this algorithm, a dedicated architecture design using the proposed CBBME algorithm is developed. With certain optimisation and design considerations, the memory access and processing cycles can be reduced. The average number of clock cycles for the processing of one binary alpha block is only 1708, which is only 56% of the previous design. In addition, a prototyping chip for shape coding is implemented and verified. The die area is 2.4×2.4 mm2 with TSMC 0.18 µm CMOS technology and the maximum clock frequency is 53 MHz.

Early Termination Scheme for Binary Block Motion Estimation

For real-time video encoder, low-complexity video encoding algorithms are required in many applications. This paper provides an early termination scheme to make the conventional binary block motion estimation algorithm significantly faster. The difference between the intensity of original frame and its filtered version is used as an input to something in this paper. With video codec, the proposed scheme shows improved visual quality while reducing complexity. Experimental results are provided to compare the performance of the proposed scheme with the conventional algorithms.

Binary Motion Estimation with Hybrid Distortion Measure

This paper proposes a new binary motion estimation algorithm that improves the motion vector accuracy by using a hybrid distortion measure. Unlike conventional binary motion estimation algorithms, the proposed algorithm considers the sum of absolute difference (SAD) as well as the sum of bit-wise difference (SBD) as a block-matching criterion. In order to reduce the computational complexity and remove additional memory accesses, a new scheme is used for SAD calculation. This scheme uses 8-bit data of the lowest layer already moved into the local buffer to calculate the SAD of other higher binary layer. Experimental results show that the proposed algorithm finds more accurate motion vectors and removes the blockishness of the reconstructed video effectively. We applied this algorithm to existing video encoder and obtained noticeable visual quality enhancement.

Block motion estimation using adaptive modified two-bit transform

An adaptive modification to the two-bit transform-based low-complexity block motion estimation approach is proposed. Initially, video frames are converted into two-bit representations using the two-bit transform (2BT), and binary block-based motion estimation is performed using these two bit-planes. Modification to the original 2BT-based motion estimation scheme is introduced by conditional local or full searches using the mean absolute difference criterion to improve the initial motion estimation accuracy. The condition threshold is adaptively varied according to block detail using the block variance already computed for the 2BT process. Experimental results show that the proposed adaptive modified 2BT-based motion estimation technique can significantly improve peak signal-to-noise ratio performance compared with 2BT only motion estimation, and outperforms modified one-bit transform (1BT)-based motion estimation as well as modified 2BT-based motion estimation without adaptation at the same motion estimation cost. The main contribution of this work is to provide an adaptive decision on whether a modified search should be carried out after the low-complexity motion estimation process.

Energy-Efficient Acceleration of MPEG-4 Compression Tools

We propose novel hardware accelerator architectures for the most computationally demanding algorithms of the MPEG-4 video compression standard-motion estimation, binary motion estimation (for shape coding), and the forward/inverse discrete cosine transforms (incorporating shape adaptive modes). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09 µm TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art.

An Efficient Binary Motion Estimation Algorithm and its Architecture for MPEG-4 Shape Encoding

This paper presents a fast binary motion estimation (BME) algorithm and its architecture for MPEG-4 shape encoding. The proposed algorithm explores the property of the binary-value in BME to quickly skip the unnecessary sum of absolute differences (SAD) computation. When comparing with the full search algorithm, simulation results show that it can efficiently save in the search positions to an average <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-hbox99.58$</tex> % of that in the full search algorithm with the same PSNR quality. Due to the algorithm's simplicity and regularity, the resulting hardware implementation also exhibits simple and regular control and data flow. It can achieve real-time encoding with only 11582 gate count.

Two-bit transform for binary block motion estimation

One-bit transforms (1BTs) have been proposed for low-complexity block-based motion estimation by reducing the representation order to a single bit, and employing binary matching criteria. However, as a single bit is used in the representation of image frames, bad motion vectors are likely to be resolved in 1BT-based motion estimation algorithms particularly for small block sizes. It is proposed in this paper to utilize a two-bit transform (2BT) for block-based motion estimation. Image frames are converted into two-bit representations by a simple block-by-block two bit transform based on multithresholding with mean and linearly approximated standard deviation values. In order to avoid blocking effects at block boundaries during the block-by-block transformation while enabling the two-bit representation to be constructed according to local detail, threshold values are computed within a larger window surrounding the transforming block. The 2BT makes use of lower bit-depth and binary matching criteria properties of 1BTs to achieve low-complexity block motion estimation. The 2BT improves motion estimation accuracy and seriously reduces the amount of bad motion vectors compared to 1BTs, particularly for small block sizes. It is shown that the proposed 2BT-based motion estimation technique improves motion estimation accuracy in terms of peak signal-to-noise ratio of reconstructed frames and also results in visually more accurate frames subsequent to motion compensation compared to the 1BT-based motion estimation approach.

DCT-based adaptive thresholding algorithm for binary motion estimation

This paper presents a discrete-cosine transform (DCT)-based adaptive thresholding algorithm to achieve an effective binarization of video image for binary motion estimation (BME). The BME through the full search mechanism requires extremely low hardware complexity. Experimental results show that the proposed adaptive BME attains performance close to the 8-bit resolution ME for low motion sequences with full search strategy. Compared to the well-known single-layer BME, the proposed adaptive algorithm shows better peak signal-to-noise ratio performance and more robustness to complex images. Moreover, the proposed algorithm has a lower computational complexity that is suitable for VLSI implementation with a smaller hardware overhead.

A Fast Binary Motion Estimation Algorithm for MPEG-4 Shape Coding

This paper presents a fast binary motion estimation (BME) algorithm using diamond search pattern for MPEG-4 shape coding, which is the key technology for supporting the content-based video coding. Based on the properties of binary shape information, a boundary mask for efficient search positions can be generated. Therefore, a large number of search points can be skipped. Simulation results show that our algorithm combined with diamond shaped zones takes equal bit rate in the same quality but reduces the number of search points marvelously in BME to 0.6% compared with full search algorithm, which is described in MPEG-4 verification mode. The proposed algorithm will reduce computational complexity of shape coding significantly and be suitable for real-time software and hardware applications of MPEG-4 shape coding.

A novel all-binary motion estimation (ABME) with optimized hardware architectures

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.

VLSI Architecture for Fast Motion Estimation Based on Bit-Plane Matching

In this paper, we propose a VLSI architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation using 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using simple Boolean functions only, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By contolling the data ow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory), so that we can remove the time overhead for accessing the local memory and/or adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6m triple-metal CMOS chip of size 8:15 10:84mm. Index Terms Video Compression, Fast Motion Estimation, VLSI Architecture

New fast binary pyramid motion estimation for MPEG2 and HDTV encoding

A novel fast binary pyramid motion estimation (FBPME) algorithm is presented in this paper. The proposed FBPME scheme is based on binary multiresolution layers, exclusive-or (XOR) Boolean block mat...

New fast binary pyramid motion estimation for MPEG2 and HDTV encoding

A novel fast binary pyramid motion estimation (FBPME) algorithm is presented in this paper. The proposed FBPME scheme is based on binary multiresolution layers, exclusive-or (XOR) Boolean block matching, and a N-scale tiling search scheme. Each video frame is converted into a pyramid structure of K-1 binary layers with resolution decimation, plus one integer layer at the lowest resolution. At the lowest resolution layer, the N-scale tiling search is performed to select initial motion vector candidates. Motion vector fields are gradually refined with the XOR Boolean block-matching criterion and the N-scale tiling search schemes in higher binary layers. FBPME performs several thousands times faster than the conventional full-search block-matching scheme at the same PSNR performance and visual quality. It also dramatically reduces the bus bandwidth and on-chip memory requirement. Moreover, hardware complexity is low due to its binary nature. Fully functional software MPEG-2 MP@ML encoders and Advanced Television Standard Committee high definition television encoders based on the FBPME algorithm have been implemented. FBPME hardware architecture has been developed and is being incorporated into single-chip MPEG encoders. A wide range of video sequences at various resolutions has been tested. The proposed algorithm is also applicable to other digital video compression standards such as H.261, H.263, and MPEG4.