A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture

Abstract

Higher quality video encoding is only one of many requirements in an industry increasingly interested in lower power consumption, upgradable standards flexibility, and lower cost. To date, meeting all needs at the same time has been unachievable, limited by inefficiencies in underlying silicon architectures and traditional programming methodologies. Legacy processing solutions using arrays of field programmable gate arrays (FPGAs), digital signal processors (DSPs), general purpose processors (GPPs), or inflexible application specific integrated circuits (ASICs) have forced designers to make feature set tradeoffs and solutions that do not scale well with increasing pixel rates. A new approach using a dataflow programming methodology and a massively parallel processor array introduces a step in improvement in meeting tomorrow's equipment requirement with respect to computationally intensive algorithms such as H.264 Hi10P, Level 4.1 or greater. This development flow allows for (1) rapid deployment, (2) software-defined implementation that is upgradable for new features or algorithm enhancements, and (3) high-quality/low power video encoding at the point of capture. We present two key components of an H.264 encoder—Context Adaptive Binary Arithmetic Coding (CABAC) and motion estimation—and demonstrate the application of the dataflow methodology on a massively parallel processor.