Binary Logic Circuits Research Articles

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Multiple Value Logic (MVL) circuits in high-speed digital systems can represent significantly more information than traditional binary logic circuits. The increasing demand for enhanced data storage capacity has driven the adoption of MVL circuits. However, designing MVL circuits presents challenges, particularly in achieving improved performance aligned with the desired threshold voltage. To address this challenge, harnessing carbon nanotube field-effect transistors (CNTFETs) has been instrumental in designing MVL circuits. CNTFETs offer distinct advantages due to their large resistors. Furthermore, substituting these resistors with Resistive Random Access Memory (RRAM) to implement Ternary logic circuits enhances storage capacity by enabling multiple resistance states within a single cell. This paper presents a novel MVL circuit design that leverages the unique characteristics of CNTFETs and RRAM. Additionally, gate implementation is explored using a Recurrent Neural Network − Long-Short Term Memory (RNN-LSTM) based Tasmanian Devil Optimization algorithm. The practical implementation uses Synopsis HSPICE software with CNTFET technology at 32 nm. A comprehensive performance analysis compares this approach with state-of-the-art solutions regarding delay, area, and power consumption. Significant reductions in area, power consumption, and transistor count are revealed with the proposed approach.

A review on multiple-valued logic circuits

Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.

Ternary combinational logic gate design based on tri-valued memristors

Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated. In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic functions through a series connection of memristors. The ternary encoder, ternary decoder, ternary comparator, and ternary data selector are implemented by this method, and the effectiveness of the circuits is verified by LTspice simulations.

Performance Enhancement of Organic Ternary Logic Circuits through UV Irradiation and Geometry Optimization

AbstractMultivalued logic (MVL) circuits offer higher information density compared with conventional binary logic circuits. However, achieving a proper balance between logic states and a low‐voltage gain remains a challenge in MVL devices. This study proposes two strategies to address this problem: using the optical absorption of organic semiconductors and optimizing device geometry. A ternary inverter is fabricated using a series circuit consisting of an antiambipolar transistor with a heterojunction of C8‐BTBT and PTCDI‐C8 semiconductors and a PTCDI‐C8 transistor. Although the inverter exhibits three distinct logic levels, it suffers from an inadequate voltage balance between the ternary logic states. To overcome this, UV light irradiation is employed first to modulate the transistor characteristics, thus improving the output voltage level and input voltage range of the logic ½ state. Subsequently, the channel length of the PTCDI‐C8 transistor is optimized to further enhance the voltage transfer characteristics of the inverter. Through these combined techniques, ideal output voltage levels are achieved for all three logic states along with an enhanced voltage gain during the transition from the logic ½ state to the logic 0 state. This work is thus an advancement toward reliable, efficient organic ternary logic circuits.

Multiple stimuli-switchable electrocatalysis and logic gates of l-cysteine based on P(DEA–co-VPBA) hydrogel films

In this work, poly(N',N-diethylacrylamide-co-4-vinylphenylboronic acid) (P(DEA-co-VPBA)) hydrogel films were successfully assembled on the pyrolytic graphite (PG) electrode by a simple radical polymerization. Reversible thermal, glucose and pH-triggered electrochemical reactions were obtained in the presence of 1,1′-ferrocene dicarboxylic acid (FDA) with electro-redox properties. The thermal response performances of the thin-film electrode were attributed to the PDEA component, the sensitive behaviors of glucose were ascribed to the VPBA component, and the sensitive behaviors of pH were affected by PDEA and VPBA. The electrocatalytic oxidation of l-cysteine by FDA on the hydrogel film electrodes significantly enhanced the difference between the on and off states of the multi-response cyclic voltammetry (CV) signals. This smart polymer hydrogel film electrode with amplified signals could be further used to realize a 4-input/9-output binary logic circuit, which was constructed with temperature, glucose, pH, and cysteine as inputs and different levels of Ipa and Ipc responses as outputs. Furthermore, a 2-to-4 decoder, a 4-to-2 encoder, and a 4-input keypad lock were built on the same platform. This polymer electrocatalysis system provides a novel idea for constructing complex biological computing systems.

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

Quaternary Logic Circuits Based on Low-Voltage Programmable/Erasable Four-Level Organic Transistor Nonvolatile Memories

Developing the multi-valued logic circuits, that can handle more data than the conventional binary logic circuits, is a promising strategy to break through the well-known Moore’s law. In this letter, we demonstrate quaternary logic circuits, for the first time, based on the four-level organic thin-film transistor nonvolatile memories (OTFT-NVMs) as the core components. High-performance four-level OTFT-NVMs are achieved, with the low programming/erasing voltages of ±15 V, high mobility up to 7.4 cm2/Vs, reliable endurance, and stable retention capabilities. By connecting the four-level OTFT-NVMs with a load resistance in the reasonable ways, we build the logic circuits to reliably perform quaternary logic operations of NOT, NAND and NOR, respectively. Our works lay the foundation to develop the novel quaternary integrated circuits in hardware.

Hysteresis and turn-on voltage tailoring of indium gallium zinc oxide transistors by employing a sandwiched structure with indium oxide

• Transistor with ternary oxide semiconductor shows large hysteresis at low voltage. • Hysteresis can be addressed by improving semiconductor-dielectric interface. • Forming a sandwich structure with In 2 O 3 reduces hysteresis. • Turn-on voltage of transistors is controlled via the In 2 O 3 film thickness. Transparent electronics with low power consumption is an important area of research for the display industry. Operating voltages of transistors can be successfully reduced by employing gate dielectrics with high dielectric constants. However, interfacial trap sites between dielectric and semiconductor layers might cause hysteresis. Here, transistors were fabricated using amorphous indium gallium zinc oxide (a-IGZO, molar ratio of In:Ga:Zn 1:1:1), a transparent semiconductor with high electron mobility. When prepared on top of Al 2 O 3 gate dielectric, drain current was found to depend on the direction of the gate sweep. A stacked active layer was prepared with the a-IGZO being sandwiched between In 2 O 3 thin films to mitigate the hysteresis of the device. Moreover, it was found that by varying the In 2 O 3 layer thickness, the device fabrication can be optimized to improve the device-to-device reproducibility of the charge carrier mobility. Additionally, the turn-on voltage, a crucial parameter of transistors in binary logic circuits, improved significantly when using the optimized layer structure.

Linear Algebra Elucidates Class-E Power Amplifiers [Educator’s Corner

Power amplifiers are generally classified into two categories, one of which collects linear amplifiers, such as class A and push-pull class B. They behave in an analog manner, i.e., the input signal waveform remains unchanged through amplification. Therefore, they are usually characterized under a small-signal assumption. The other category collects saturated amplifiers, such as classes D, E, and F. They employ an active device that behaves as a quickly alternating on-off switch, like the one used in binary-logic circuits. This switch-mode operation brings an extremely high dc-to-RF power conversion efficiency. In particular, a class-E amplifier works for high-power broadcasting, radio communication, and recently, emerging wireless power transfer applications. With this background, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Microwave Magazine</i> ’s July/August 2018 special issue was on class-E amplifiers <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> .

WITHDRAWN: Modified multi mode digital modulator using ternary logic

With the increasing demand for high density digital logic circuits in an IC, the binary logic circuits have more interconnect density, which increases power consumption. One suitable solution to reduce the number of interconnections is to use multi valued logic. With the advances in communication systems, high speed modulators are required. This paper presents a modified multi mode digital modulator using ternary logic. This modulator can be configured as ASK, FSK and PSK. In this modulator, the number of ternary multiplexers is reduced. This modified architecture saves 80% of power consumption and 31% of area. All the designs are simulated using Tanner EDA.

Photo-responsive MoS2/organic-rubrene heterojunction field-effect-transistor: application to photo-triggered ternary inverter

Multivalued logic (MVL) circuits with higher efficiencies, such as the ternary inverter, can be considered as promising structures to overcome the limitation of a binary system. Photo-responsive characteristics of the two-dimensional (2D) MoS2 and the organic-rubrene nanosheet (NS) n-p heterojunction field-effect-transistor (FET) are studied with the aim to construct a novel photo-triggered ternary inverter as a MVL circuit. Anti-ambipolar transistor (AAT) characteristics were observed for the MoS2/organic-rubrene-NS n-p heterojunction FETs. The serially connected devices comprising the AAT with a single MoS2 (n-type)-based FET or with a single rubrene-NS (p-type)-based FET were fabricated to investigate inverter characteristics, which can be advantageous compared to the conventional complementary metal-oxide semiconductor employed in a binary logic circuit. Interestingly, the inverters employing the AAT connected to the p-type rubrene-NS-based FET in series were successfully operated as MVL circuits under light irradiation. The characteristics of new photo-triggered ternary inverters originate from the distinct photo-responsivity of p-type organic-rubrene-NS as well as the positive shift of the threshold voltage of the AAT and p-type rubrene-NS-based FET based on the photo-gating effect, achieved under specific light-irradiation conditions. In this work, a new photo-triggered (i.e. photo-driven) ternary inverter using 2D-MoS2 and organic semiconducting rubrene-NS heterojunction FETs was successfully realized. The heterojunctions of 2D inorganic and organic semiconductors exhibit great potential toward the development of new photo-responsive MVL circuits and multifunctional transistors with extraordinary characteristics and performance including energy saving.

Multi-Valued Logic Circuits Based on Organic Anti-ambipolar Transistors.

Multivalued logic circuits, which can handle more information than conventional binary logic circuits, have attracted much attention as a promising way to improve the data-processing capabilities of integrated circuits. In this study, we developed a ternary inverter based on organic field-effect transistors (OFET) as a potential component of high-performance and flexible integrated circuits. Key elements are anti-ambipolar and n-type OFETs connected in series. First, we demonstrate an organic ternary inverter that exhibits three distinct logic states. Second, the operating voltage was greatly reduced by taking advantage of an Al2O3 gate dielectric. Finally, the operating voltage was finely tuned by the designing of the device geometry. These results are achievable owing to the flexible controllability of the device configuration, suggesting that the organic ternary inverter plays an important role with regard to high-performance organic integrated circuits.

Redox Active Binary Logic Gate Circuit for Homeland Security.

Bipolar junction transistors are at the frontiers of modern electronics owing to their discrete voltage regulated operational levels. Here we report a redox active binary logic gate (RLG) which can store a "0" and "1" with distinct operational levels, albeit without an external voltage stimuli. In the RLG, a shorted configuration of half-cell electrodes provided the logic low level and decoupled configuration relaxed the system to the logic high level due to self-charge injection into the redox active polymeric system. Galvanostatic intermittent titration and electrochemical quartz crystal microbalance studies indicate the kinetics of self-charge injection are quite faster and sustainable in polypyrrole based RLG, recovering more than 70% signal in just 14 s with minor signal reduction at the end of 10000 cycles. These remarkable properties of RLGs are extended to design a security sensor which can detect and count intruders in a locality with decent precision and switching speed.

Organotitania-Based Nanostructures as a Suitable Platform for the Implementation of Binary, Ternary, and Fuzzy Logic Systems.

Titanium dioxide nanocomposites were synthesized in hierarchical architectures through the use of a 1,4-dihydroxyanthraquinone photosensitizer. In the first step, the dye was either incorporated into the TiO2 core or adsorbed on its surface. In the subsequent phase, both structures were covered with an outer layer of titanium dioxide. The structure, morphology, aggregation, spectroscopic, and electrochemical properties of the synthesized TiO2 -based materials are presented with emphasis on the photosensitization and the photocurrent switching phenomena, which are also discussed within the context of the optical logic gates implementation and fuzzy logic systems operation. We present three different interpretations of the photocurrent action spectra yielding binary, ternary, or fuzzy logic circuits.

A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs

Using multiple-valued logic provides more information transmission over a signal line. So it could solve the binary logic circuits problems such as interconnections requirement. In this paper, a un...

A Novel Quaternary Full Adder Cell Based on Nanotechnology

Binary logic circuits are limited by the requirement of interconnections. A feasible solution is to transmit more information over a signal line and utilizing multiple-valued logic (MVL). This paper presents a novel high performance quaternary full adder cell based on carbon nanotube field effect transistor (CNTFET). The proposed Quaternary full adder is designed in multiple valued voltage mode. CNTFET is a promising candidate for replacing MOSFET with some useful properties, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, which make them very appropriate for voltage mode multiple threshold circuits design. The proposed circuit is examined, using Synopsys HSPICE with the standard 32 nm CNTFET technology with different temperatures and supply voltages.

Low voltage low power programmable logic gate based on SE-MOSFET

Single electron transistor (SET) is one of the most promising devices for nanoscale circuit design. In this paper, new low voltage low power programmable logic gate circuits using SE-MOSFET are presented. Devices that combine singleelectronand metal–oxide–semiconductor (MOS) transistors allows compact realization of basic logic function that exhibit periodic transfer characteristics. The proposed SE-MOSFET logic gates are useful for implementing binary logic circuits. The proposed programmable logic gate is verified by simulating the circuit using PSPICE. The results show that the operation of proposed circuit is in accordance with the theories.

A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations

Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

Multi-Valued Logic Circuits Using Hybrid Circuit Consisting of Three Gates Single-Electron Transistors (TG-SETs) and MOSFETs

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values.