Binary Frequency Divider Research Articles

GaAs Integrated Logic with Normally-Off MESFETs

The normally-off GaAs MESFET digital integrated circuits which feature power dissipation as low as 0.2 mW per gate and sub-nanosecond delay time have been developed. To investigate the power-speed performance of the ICs, ring oscillators with different fan-in/fan-out have been fabricated. For fan-in/fan-out = 1/1 , a propagation delay time is typically 250 ps with a power-delay product of 40 fJ. For fan-in/fan-out = 2/2, the delay time and PD product increase to 430 ps and 97 fJ, respectively. A binary frequency divider with a master-slave flip-flop has been fabricated. Maximum counting frequency was 610 MHz with supply voltage of 1.5 V. Equivalent delay time per gate and PD product are 410 ps and 85 fJ, respectively. By shortening gate length, the operating range of the ICs will be expanded to G bit/s area.

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.

An Adjustable Binary Frequency Divider

An Adjustable Binary Frequency Divider

A New Reference Frecpiency Standard for the L Multiplex System

Four precision quartz crystal oscillators form the heart of a new solid-state precision frequency standard, designed to meet the requirements of the present and next generation of L multiplex carrier equipment. The output frequencies of 64 and 512 kHz are derived from the 4.096-MHz oscillator outputs by binary frequency dividers. A master and standby divider chain form a redundant path linking two of the oscillators and the passive output distribution circuits. Intentional transfers between master and standby channels can be made without introducing significant phase hits at the output. Automatic transfer between channels occurs upon a catastrophic loss of the output signal. Two additional oscillators and dividers are provided as “hot spares” which can be manually patched into service. Critical points in the system are monitored by major and minor alarm circuits, and a very low frequency receiver-comparator provides a means for maintaining the oscillator frequencies to within one part in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> of a vlf standard frequency broadcast.

Approach to the synthesis of networks realized with binary frequency dividers

The problem of the synthesis of networks formed with capacitively coupled flip-flops is investigated. A method is described, which allows to establish whether a machine of the above type exists, which realizes the state sequence of an arbitrary transition table and, in the affirmative case, to build it up.

Behaviour of networks realized with binary frequency dividers

In the present paper the properties of networks realized with binary frequency dividers (capacitively coupled flip-flops) have been investigated. Arbitrary connections among the flip-flops are considered. Making use of a simple model of the nets and of the flip-flops, a simple method of analysis has been developed, which makes use of a step by step procedure Following it, it has been shown how to determine the state sequence for multi-input networks. It is also shown that the considered nets may be unstable. To investigate further their nature, in order to put in evidence the general properties, a synthetic approach has been developed. So it has been possible not only to show that the considered networks are either stable or not, but also to give the stability criterion. When a net is stable, there exists at least a periodic part of its state sequence; if more periodic sequences exist, their periods are the same. A method to determine the period is given. Following this method, it has been possible to develop a simple synthesis procedure when the periodic part of the sequence is of interest. It has also been shown how the state sequence changes when the input connections are modified. At the end, some of the preceding results are discussed and extended to general frequency dividers.