Bidirectional Linear Array Research Articles

Bidirectional circularly‐polarised loop linear array fed by slotted SIW

A novel multilayer bidirectional linear array with the same sense circularly polarised (CP) radiation patterns are proposed. The CP resonant unit consists of a pair of loops and two square patches added on their opposite corners. With a feeding slotted substrate integrated waveguide (SIW) sandwiched between two back-to-back mirror rotated resonant units, a radiating element is designed, and same sense bidirectional CP waves are generated. Along the longitude direction, the radiating elements are arranged alternately from the centre line of the slotted SIW. Then, an 8-element linear array with uniform distribution is designed. Identical right-hand CP waves are achieved in both front and back directions. The array is fabricated, and measured results are in good agreement with simulated ones.

Routing and wavelength assignment for 3-ary n-cube communication patterns in linear array optical networks for n communication rounds

k-ary n-cubes are a class of communication patterns that are employed by a number of typical parallel algorithms. This paper addresses the implementation of parallel algorithms with bidirectional 3-ary n-cube communication patterns on a bidirectional linear array WDM optical networks when the information is transmitted one dimension after another. By giving an embedding scheme ϕ, we prove the optimal number of wavelengths under ϕ and design a routing and wavelength assignment strategy of it.

Speeding up the systolic design in bidirectional linear arrays

The bidirectional linear arrays were derived heuristically for various algorithms or by following the"systolic principle"introduced by H. T. Kung and C. E. Leiserson. This principle was constrained since all the data items in the data streams have to enter the array every second time moment. This was"the only"design that enables each data item to meet all the elements from the other data stream We introduce a new design, and show that the bidirectional linear array can be organizedwith data items that enter the array in consecutive time moments. The standard IPS cell isslightly modified to compute two pipelineable IPS operations instead of one. Also a specialresident memory is included in the cell. This now enables each data item to flow in the data pathand to be delayed in the same cell in the next time moment. So it can meet all the data itemsfrom the other data stream. The complete details of the cell and the algorithm are discussed andthen this design is compared to the standard BLA design It is shown that the fastest systolic BLA design offers a speedup of 2, uses half the processorsthan the standard BLA design and finally the efficiency is 4 times greater. The maximumefficiency of 100% can be exploited in all the cells, contrary to the standard BLA designs. TheMA/AR filters are the examples represented with full details. The implementation of the fastestBLA design is possible in all available processor arrays. Even the systolic WARP cell canemulate this cell, although it is designed as an implementation of the standard BLAs.

Double pipelines and fast systolic designs on linear arrays

The fast systolic computation and double pipelines were designed to achieve implementations that use less processors to execute the algorithm in less time then the conventional systolic algorithms. H. T. Kung and C. S. Leiserson in [1-3] proposed systolic algorithms realized on a bidirectional linear array where two data streams flow in opposite directions. The data flow introduced for this solution requires data elements to appear in the data stream at each second time step, which is the only way to meet all the elements from the other data stream. In [4, 5] the authors proposed a linear array where one data stream is double mapped while the elements from the other data stream flow in consecutive time moments. The procedure to obtain such a solution is called a fast systolic design. It was shown in [5] that double pipeline solutions are obtained by separating and grouping techniques in addition to this design. Several more efficient systolic designs have been proposed for the matrix vector multiplication algorithm in [4, 5]. Here we implement these techniques on other linear array algorithms such as triangular linear system solver, string comparison, convolution, correlation, MA and AR filter.

Designing of processor-time optimal systolic arrays for band matrix-vector multiplication

This paper describes the procedure for synthesizing processor-time optimal linear (1D) systolic arrays for band matrix-vector multiplication. The procedure is based on data dependence approach. By the described procedure, three different systolic arrays, denoted as S1, S2 and S3, are obtained. The first two are obtained by the orthogonal directions. The array S3 is a bidirectional linear array of Kung's type. The procedure enables us to obtain optimal bidirectional 1D systolic array where data streams enter the array in consecutive time instances which leads to decreasing of execution time and increasing of PEs' utilization

Recursive folding for efficiency improvement of systolic arrays - part I

In this paper, the mathematical theory of Recursive Folding for Processor Arrays is developed. The new theory shows that a ofold increase in efficiency of c-periodic (C=2) systolic arrays, obtained by the data dependence method, is achieved. Using c-times less processors than the original array, the new folded array is totally homogeneous and performs the algorithm in T{ot time steps, 7of < T{ot 7;ot + 2{c — 1), where Ttot is the time complexity of the original array. In the case of linear arrays, a new type of array named Switched Unidirectional Linear Array (SULA) is obtained that saves up to 50% of the communication links of the original Bidirectional Linear Array (BLA) in a special case.

THE FASTEST MATRIX VECTOR MULTIPLICATION

The design proposed here concerns bidirectional linear Very Large Scale Integration (VLSI) processor arrays. No technique has yet been developed to enable such a design where the data items enter the array in consecutive time moments. The problem to be resolved was how to organize the array and the cells to enable each data item to meet all the elements from the other data stream. The developed design shows that such an array exists and only the processor cell is slightly more complex. All other VLSI constraints for local communication and regular data flow are fulfilled. This design shows a speedup of 2 according to the standard bidirectional linear array and a 50% reduction in the number of processors used. This results in a fourfold increase in efficiency, which means that finally the limit of 100% efficiency can be reached by the bidirectional linear arrays.