Bidirectional Data Rate Research Articles

Low Complexity Resource Allocation Techniques for Symmetrical Services in OFDMA Systems

The popularity of symmetrical services like video conferencing, telemedicine etc. is in an upsurge. With the rapid increase in the number of customers for such services, the demand for reliable and computationally feasible resource allocation techniques satisfying all the users are also intensifying. This paper proposes two computationally feasible techniques for allocation of resources in OFDMA system specifically for services that demand similar quality in the uplink and downlink directions. The resource allocation problem is multiobjective in nature with the objectives to maximize the data rates in both directions meanwhile minimizing the difference in the bidirectional data rates for each user. Fairness has been incorporated as a major constraint in the formulation of the optimization problem. Equal Power allocation and weighted sum method are implemented for power allocation while subcarrier allocation is carried out using an evolutionary technique. The solution for subcarrier allocation is represented in a novel manner such that the complexity is reduced to a great extent at the same time attaining acceptable data rates.

Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

The full-duplex data communication over on-chip global interconnects suffers from large amounts of amplitude residue echo, leading to the closure of the vertical eye. This work proposes, a residue monitor enabled adaptive echo-cancellation scheme for full-duplex communication with power efficient charge-mode circuits. The proposed architecture employs charge-domain echo cancellation scheme for separating the outbound signal from the inbound signal by precisely controlling the capacitor bank output, thanks to the availability of residue monitor and high precision MOS switches and capacitors at sub-100 nm technology nodes. The residue monitor in the loop tracks the amount of amplitude residue and then sets the control bits, when the loop is locked. Further, this work proposes power efficient charge-mode circuits based replica generation stage, which does not contribute to additional power consumption like in the conventional echo-cancellation schemes. The proposed scheme is implemented at the architectural level with behavioural modeling in Verilog-AMS and also at the circuit level in 1.2 ​V, 65-nm CMOS Technology. The behavioural simulations shows that the residue monitor loop is getting locked while tracking the control voltage generated by the charge regulator for the target near-zero amplitude residue and accordingly control bits to the capacitor bank are set. Circuit level performance shows the functioning at a bidirectional data rate of 20 Gbps over a 1-mm on-chip global interconnect and the extracted received signal has 149 ​mV differential swing at a power consumption of 9.64 ​mW.

Resource allocation algorithm for symmetrical services in OFDMA systems

<p><span>The widespread acceptance of symmetrical services has urged for performance betterment techniques in wireless communication systems. In this paper, we propose an algorithm for resource allocation in MIMO-OFDMA system for applications that demand similar quality in uplink and downlink direction. The problem is formulated as multiobjective optimization problem with objectives to maximize the bidirectional data rates for individual users and to minimize the difference between the uplink and downlink data rate for each user. Fairness has been considered as a constraint in the optimization problem. The power allocation for each subcarrier in the OFDMA system is carried out using Linear Programming (LP) techniques, while the subcarrier allocation problem has been undertaken using an innovative multiobjective optimization technique that employs the concept of non-dominance in evolutionary algorithms. The results are extremely encouraging as they outperform the algorithms reported in literature using linear programming techniques or evolutionary algorithms solely. </span></p>

Performance of Network-Assisted Full-Duplex for Cell-Free Massive MIMO

Network assisted full-duplex (NAFD) is a spatial-division duplex technique for future wireless networks with cell-free massive multiple-input multiple-output (CF massive MIMO) network, where a large number of remote antenna units (RAUs), either using half-duplex or full-duplex, jointly support truly flexible duplex including time-division duplex, frequency-division duplex and full duplex on demand of uplink and downlink traffic by using network MIMO methods. With NAFD, bi-directional data rates of the wireless network could be increased and end-to-end delay could be reduced. In this paper, the spectral efficiency of NAFD communications in CF massive MIMO network with imperfect channel state information (CSI) is investigated under spatial correlated channels. Based on large dimensional random matrix theory, the deterministic equivalents for the uplink sum-rate with minimum-mean-square-error (MMSE) receiver as well as the downlink sum-rate with zero-forcing (ZF) and regularized zero-forcing (RZF) beamforming are derived. Numerical results show that under various environmental settings, the deterministic equivalents are accurate in both a large-scale system and system with a finite number of antennas. It is also shown that with the downlink-to-uplink interference cancellation, the uplink spectral efficiency of CF massive MIMO with NAFD could be improved. The spectral efficiencies of NAFD with different duplex configurations such as in-band full-duplex, and half-duplex are compared. With the same total numbers of transmit and receive antennas, NAFD with half-duplex RAUs offers a higher spectral efficiency. To alleviate the uplink-to-downlink interference, a novel genetic algorithm based user scheduling strategy (GAS) is proposed. Simulation results show that the achievable downlink sum-rate by using the GAS is greatly improved compared to that by using the random user scheduling.

A Novel Genetic Resource Allocation Algorithm for Symmetrical Services in OFDMA Systems

Performance enhancement of symmetrical services has been very essential today owing to the widespread acceptance and demand of these services in the present generation communication systems. An algorithm with reduced complexity for subcarrier allocation in OFDMA/SC-FDMA system for specific applications that demand similar bidirectional quality is proposed in this paper. The resource allocation problem devised is a multiobjective optimization problem with objectives to maximize bidirectional data rates and minimize the difference in bidirectional data rates, with fairness as a significant constraint. The original problem is mathematically intractable due to non-convexity and therefore linear programming techniques fail to find an optimal solution. The subcarrier allocation problem has been undertaken using an innovative multiobjective optimization technique that employs the concept of non-dominance in evolutionary algorithms. The results are extremely encouraging, while significantly reducing the complexity involved in the processing of algorithm.

A Transportable Reflectarray Antenna for Satellite Ku-band Emergency Communications

The design of a Ku-band reconfigurable reflectarray antenna for emergency satellite communications is presented. Bidirectional high data rate satellite links are needed in emergency conditions where other telecommunication infrastructures are not available. In order to operate in this type of scenario, an antenna should be deployable, transportable, and easily repointable. The need of an automatic and fast satellite location and pointing system leads to a completely electronic reconfigurable antenna. The operative bandwidth is from 10.7 to 12.5 GHz for reception and from 14 up to 14.5 GHz for transmission (30% of relative bandwidth). The selected antenna architecture is based on a dual reflectarray system comprising a passive subreflectarray and an active main reflectarray made of reconfigurable 1-bit elementary cells based on PIN diodes.

Ultra-Dense, Single-Wavelength DFT-Spread OFDMA PON With Laserless 1.2 Gb/s ONU Ready for Silicon Photonics Integration

We introduce an ultra-dense network architecture designed for silicon photonics at the optical network unit (ONU). This network relies on only 3.333 GSa/s and 417 MSa/s converters at the OLT and ONU, respectively, and offers up to 12 Gbit/s of symmetric traffic in a single 12.5-GHz optical channel. Multiple access and lowest processing speeds at the ONU are enabled by choosing 10 DFT-spread OFDM subbands. We demonstrate this FDMA network architecture in a proof-of-principle experiment with up to eight 300-MBd 16QAM subbands offering a bidirectional data rate of 9.6 Gb/s. Real-time signal processing is realized for downstream transmission. Finally, we shortly address future improvements of this network architecture by employing integrated silicon photonics and analog signal processing to enable fine FDM for next-generation access networks.

A Surface Mounting Embedded Optical Transceiver with Bi-Directional Data Rate of Eight Channels × 10 Gbps

The bi-directional data rate is investigated of an eight-channel × 10-Gbps optical transceiver with a size of 15 mm × 15 mm × 6 mm and ball grid array package form that was designed and fabricated. A passive optical coupling method is designed based on a coupling lens array, which is transformed to substrate through a carrier. This electrical performance is characterized through a 3D full wave simulation and shows great advantages compared with traditional pluggable optical transceivers. Experimental eye diagram measurement in loop-back mode via a 2-m-long multi-mode fiber array shows an eye width of 51.984 ps at a bit-error rate order of 10−12, which proves the transceiver's ability for 10.3125-Gbps data transmission.

동축 케이블과 초광대역 기술을 이용한 양방향 데이터 전송 시스템 개발

본 논문에서는 IEEE 802.15.3 Medium Access Control Layer(MAC)와 UWB PHY(Physical Layer)의 기반에서 유/무선 통신이 가능한 동축 케이블 기반의 데이터 전송 시스템을 설계하고 구현하였다. 구현된 시스템은 가정용 동축 케이블(Coaxial Cable)이나 광동축 혼합망(Hybrid Fiber Coax) 기반에서 기가비트(Gigabit) 전송률로 양방향 데이터 전송이 가능하다. 본 동축케이블 기반의 송수신 시스템은 가정이나 사무실의 75Ω 동축 케이블로 명령, 제어 그리고 데이터가 송수신 된다. 구현된 시스템은 중심 주파수 4GHz에서 1.33GHz의 대역폭으로 동작하며, BPSK를 사용하여 채널 전력의 ±15dBm으로 심벌을 송신한다. 개발된 시스템을 일반적인 가정환경 내에서의 실험 조건으로 최대 3개의 CATV RF 분배기를 통해 동작함을 확인하였다.

Terabit/s-Class Optical PCB Links Incorporating 360-Gb/s Bidirectional 850 nm Parallel Optical Transceivers

We report here on the design, fabrication, and characterization of highly integrated parallel optical transceivers designed for Tb/s-class module-to-module data transfer through polymer waveguides integrated into optical printed circuit boards (o-PCBs). The parallel optical transceiver is based on a through-silicon-via silicon carrier as the platform for integration of 24-channel vertical cavity surface-emitting laser and photodiode arrays with CMOS ICs. The Si carrier also includes optical vias (holes) for optical access to conventional surface-emitting 850 nm optoelectronic devices. The 48-channel 3-D transceiver optochips are flip-chip soldered to organic carriers to form transceiver optomodules. Fully functional optomodules with 24 transmitter + 24 receiver channels were assembled and characterized with transmitters operating up to 20 Gb/s/ch and receivers up to 15 Gb/s/ch. At 15 Gb/s, the 48-channel optomodules provide a bidirectional aggregate bandwidth of 360 Gb/s. In addition, o-PCBs have been developed using a 48-channel flex waveguide assembly attached to FR4 electronic boards. Incorporation of waveguide turning mirrors and lens arrays facilitates optical coupling to/from the o-PCB. Assembly of optomodules to the o-PCB using a ball grid array process provides both electrical and optical interconnections. An initial demonstration of the full module-to-module optical link achieved >; 20 bidirectional links at 10 Gb/s. At 15 Gb/s, operation at a bit error ratio of <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">- 12</sup> was demonstrated for 15 channels in each direction, realizing a record o-PCB link with a 225 Gb/s bidirectional aggregate data rate.

An Inside Body Power and Bidirectional Data Transfer IC Module Pair

An IC module pair utilizing only three wires was designed for biomedical implants with a master unit (MU) and a small, lightweight satellite unit (SU). Power was delivered from the MU to the SU using a three-phase signal and converted to dc in the SU IC module by a passive MOS ac-dc converter. Bidirectional data transfer between the two units was achieved by modulating the amplitudes (at periods that do not affect power delivery) and the positions of the rising and falling edges of the three-phase signal. A bidirectional data rate in the range of MB/s and an overall power efficiency of 90.2% for a 2.84-mW load were achieved in a 0.18-μm CMOS process.

A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single “Holey” CMOS IC

We report here on the design, fabrication, and high-speed performance of a compact 48-channel optical transceiver module enabled by a key novel component: a “holey” Optochip. A single CMOS transceiver chip with 24 receiver (RX) and 24 laser diode driver circuits, measuring 5.2 mm × 5.8 mm, becomes a holey Optochip with the fabrication of forty-eight through-substrate optical vias (holes): one for each transmitter (TX) and RX channel. Twenty-four channel, 850-nm VCSEL and photodiode arrays are directly flip-chip soldered to the Optochip with their active devices centered on the optical vias such that optical I/O is accessed through the substrate of the CMOS IC. The holey Optochip approach offers numerous advantages: 1) full compatibility with top emitting/detecting 850-nm VCSELs/PDs that are currently produced in high volumes; 2) close integration of the VCSEL/PD devices with their drive electronics for optimized high-speed performance; 3) a small-footprint, chip-scale package that minimizes CMOS die cost while maximizing transceiver packing density; 4) direct coupling to standard 4 × 12 multimode fiber arrays through a 2-lens optical system; and 5) straightforward scaling to larger 2-D arrays of TX and RX channels. Complete transceiver modules, or holey Optomodules, have been produced by flip-chip soldering assembled Optochips to high-density, high-speed organic carriers. A pluggable connector soldered to the bottom of the Optomodule provides all module electrical I/O. The Optomodule footprint, dictated by the 1-mm connector pitch, is 21 mm × 21 mm. Fully functional holey Optomodules with 24 TX and 24 RX channels operate up to 12.5 Gb/s/ch achieving efficiencies (including both TX and RX) of 8.2 pJ/bit. The aggregate 300-Gb/s bi-directional data rate is the highest ever reported for single-chip transceiver modules.

160 Gb/s Bidirectional Polymer-Waveguide Board-Level Optical Interconnects Using CMOS-Based Transceivers

We have developed parallel optical interconnect technologies designed to support terabit/s-class chip-to-chip data transfer through polymer waveguides integrated in printed circuit boards (PCBs). The board-level links represent a highly integrated packaging approach based on a novel parallel optical module, or Optomodule, with 16 transmitter and 16 receiver channels. Optomodules with 16 Tx+16 Rx channels have been assembled and fully characterized, with transmitters operating at data rates up to 20 Gb/s for a 27-1 PRBS pattern. Receivers characterized as fiber-coupled 16-channel transmitter-to-receiver links operated error-free up to 15 Gb/s, providing a 240 Gb/s aggregate bidirectional data rate. The low-profile Optomodule is directly surface mounted to a circuit board using convention ball grid array (BGA) solder process. Optical coupling to a dense array of polymer waveguides fabricated on the PCB is facilitated by turning mirrors and lens arrays integrated into the optical PCB. A complete optical link between two Optomodules interconnected through 32 polymer waveguides has been demonstrated with each unidirectional link operating at 10 Gb/s achieving a 160 Gb/s bidirectional data rate. The full module-to-module link provides the fastest, widest, and most integrated multimode optical bus demonstrated to date.

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.

Flat Array Antennas for Ku-Band Mobile Satellite Terminals

This work presents the advances in the development of two innovative flat array antennas for Ku-band mobile satellite terminals. The first antenna is specifically conceived for double-deck trains to allow a bi-directional high data rate satellite link. The available circular surface (diameter 80 cm) integrates both a transmitting and a receiving section, operating in orthogonal linear polarizations. The TX frequency range is fully covered while the RX bandwidth is around 1 GHz arbitrarily allocated on the DVB range depending on requirements. The beam is steered in elevation through a phased array architecture not employing costly phase shifters, while the steering in azimuth is mechanical. Active BFNs allow excellent performance in terms of EIRP and G/T, maintaining extremely low profile. High antenna efficiency and low fabrication cost are ensured by the employment of innovative SIW (Substrate Integrated Waveguide) structures. The second antenna, receiving-only, is designed for radio/video streaming services in mobile environment. Full DVB coverage is achieved thanks to cavity-backed patches operating in double linear polarization. Two independent broadband active BFNs allow simultaneous reception of both polarizations with full tracking capabilities and a squintless beam steering from to in elevation. A minimum gain of 20 dBi and G/T &gt; dB/ are achieved, while maintaining extremely compact size and flat profile. In the design of both antennas fabrication cost is considered as a driving factor, yet providing high performance with a flat profile and thus resulting in a great commercial potentiality.

Low-Power Transceiver Analog Front-End Circuits for Bidirectional High Data Rate Wireless Telemetry in Medical Endoscopy Applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.