BiCMOS Gate Research Articles

Characterization of 0.5 µm BiCMOS Gate Oxide Using Time Dependent Dielectric Breakdown Test

This paper presents Time Dependent Dielectric Breakdown (TDDB) testing of gate oxide on 0.5µm BiCMOS Technology. The gate oxide quality for the technology has been investigated and furthermore to qualify the whole set up of the foundry from the process, equipment, cleanroom control and raw material used to produce high quality gate oxide and hence good quality of BiCMOS devices. TDDB test is the most widely used testing to check the quality of gate oxide and in this paper the TDDB test done on MOS capacitors fabricated using 0.5 µm BiCMOS Technology. Seven consecutive qualification lots have been tested and the data shown that TDDB measurement is capable to differentiate between accepted wafer and rejected wafer. The data also shown that TDDB test was capable to characterise 0.5 µm BiCMOS gate oxide with higher yield and comparable with reference lot from other foundry fab.

Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET parameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used in conjunction with the established BiCMOS gate delay models. It is shown that the minimum delay BiCMOS circuits driving the large capacitive load, can be designed at the transit frequency limit with the reduced BJT AREA factor. The time delay calculations are presented for a typical BiCMOS circuit and comparison is made with the results simulated using SPICE.

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic

This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered gates is made. In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fan-out are identified and replaced with a lower power unbuffered (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lower-bound delay value that is calculated. Experimental results have confirmed the efficiency and utility of the proposed method. In 8-b adder or 8/spl times/8 b multiplier networks, just two iterations are sufficient to achieve a delay that is at worst within 0.6% of its final optimized value and at worst within 10% of the lower-bound value. In the design of BiCMOS networks, it is seen that a speed advantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BiCMOS gates versus using all CMOS or all BiCMOS gates and that this advantage increases with the tightness of the power constraint and with load capacitance.

BiCMOS domino: a novel high-speed dynamic BiCMOS logic

A new BiCMOS dynamic logic family is presented. The logic gates provide a significant speed-up over existing logic families, such as, CMOS, BiCMOS and dynamic CMOS for the same feature size. The proposed logic family provides a high drive capability to drive large loads at higher speeds compared with the CMOS domino logic family. The proposed logic family has power advantages, due to dynamic operation, compared with the conventional fully complementary CMOS and BiCMOS devices. It also has an area advantage compared with conventional BiCMOS gates. The proposed high-speed BiCMOS domino family provides speed improvement with existing feature size, using the existing fabrication technology. The novel high-speed dynamic BiCMOS logic implementations can significantly affect the speed of VLSI circuits including microprocessors, memories and signal processors.

Circuit analysis of BiCMOS gate delay

A circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a function of transistor parameters and power supply voltage is evaluated. The analytical predictions are compared with SPICE circuit simulation. Good agreement between the model and SPICE simulation is obtained. Twodimensional numerical device simulation is used to examine the physical insight into BiCMOS device operation.

An accurate transient model for BiCMOS gate optimization

A new BiCMOS delay expression considering high injection bipolar operation and capacitive charge effects on the previous stage is proposed in this paper. The obtained calculation procedure can be used for a wide range of circuit parameters and capacitive loads. Excellent agreement is found with HSPICE calculations. Sample results are shown for capacitive loads of 0.2 pF and 5 pF.

Modelling the BiCMOS switching delay including radiation effects

The effect of ionising radiation on the BiCMOS switching response has been studied. The radiation-induced surface recombination current in the base of the bipolar transistor and the radiation-induced resistive leakage paths in the BiCMOS structure have been modelled as functions of the interface state density and the oxide trapped charge density. Radiation effects on the MOSFET and the bipolar transistor including leakage paths in the BiCMOS structure have been incorporated into the equivalent circuit of the proposed model. A semianalytical solution of the transient response of the BiCMOS gate is obtained including high injection and high current base push-out effects. The proposed model is compared with experimental data and with MEDICI simulations, and the agreement is good over a wide range of radiation levels. The BiNMOS gate has been demonstrated to be more radiation hard as compared to the BiPMOS gate.

BiCMOS logic testing

With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application. >

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B/spl radic/F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 /spl mu/m, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e/sup 2.3/(/spl ap/10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e/sup 1.6/(/spl ap/5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants. >

Low-temperature BiCMOS gate pull-down delay analysis

Abstract Temperature-dependent BiCMOS gate delay analysis including high current transient has been developed. The model accounts for the high electric field effect in the nMOS transistor and high current effects in the bipolar transistor for a wide temperature range. In examining the switching transient of a BiCMOS driver, the base pushout mechanism exhibits a detrimental effect on the gate propagation delay at room temperature, while the current gain degradation and temperature-dependent intrinsic density are responsible for increasing the BiCMOS gate pulldown delay at low temperature. The analytical equations provide evaluation of the sensitivity of process and device parameters to circuit performance at different temperatures. Computer simulation of a BiNMOS driver using the present analysis is compared with a PISCES simulation in support of the physical reasoning.

Study of BiCMOS logic gate configurations for improved low-voltage performance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10 degrees C and sub-2 V at 110 degrees C. >

CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET. >

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISCs. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3- mu m BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V. >

CMOS-compatible lateral bipolar transistor for BiCMOS technology. II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub Tmax/, and r/sub bb'/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors. >

Defect modelling and testability analysis of BiCMOS circuits

BiCMOS is a recent integrated circuit technology that is rapidly becoming a mainstream technology supporting high-speed applications. Highly complex circuits are now realizable with such a technology, which merges bipolar and MOS devices on a single substrate. The fabrication process involves a mix of bipolar and MOS devices. These circuits must be tested to ensure that they have been processed correctly. The authors address the testability of BiCMOS circuits compared to equivalent CMOS circuits. Defects are modelled and their impacts on the behaviour of the circuits are analyzed by simulation. Faults are classified as logical faults or performance degradation faults. It is determined that BiCMOS gates are more difficult to test that the corresponding CMOS gates. Adequate fault models must therefore be constructed to improve the testability of BiCMOS circuits.

Supply voltage design tradeoffs between speed and NMOSFET reliability of half-micrometer BiCMOS gates

Voltage supply scaling for a BiCMOS gate was investigated experimentally and analytically. For half-micrometer technology, the supply voltage design tradeoffs between propagation delay and NMOSFET reliability were studied. It was found that the minimum BiCMOS operating voltage ranges from 2.5 to 3.0 V. This minimum can be explained by the sum of twice the base-emitter potential and the NMOSFET threshold voltage, due to the emitter grounded Bi-MOS structure of the BiCMOS gate. As a result, 3.3-V operation is inherently marginal for BiCMOS gates. On the other hand, NMOS reliability in the BiCMOS gate is drastically improved because effective drain voltage is reduced by the base-emitter potential. Thus, NMOSFETs with a channel length shorter by more than 0.2 mu m can be used, and this ensures reliable operation of BiCMOS gates at 5 V. In terms of the tradeoffs between gate speed and NMOS reliability, it is verified that BiCMOS gates offer the highest speed in half-micrometer design. >

A 6-ns 256-kb BiCMOS TTL SRAM

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >

High-performance BiCMOS 100 K-gate array

A BiCMOS gate array in 0.8- mu m technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 mu m/sup 2//gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106 K-gate array has been built on a 1.14-cm/sup 2/ chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90%. The gate array was used to implement a 74 K-gate filter design with testability features such as JTAG and two-phase scan. >

A feedback-type BiCMOS logic gate

The authors report on the development of a feedback-type BiCMOS logic gate using a 0.5- mu m BiCMOS technology. The propagation delay time of a three-input NAND gate with a 0.93-pF load is 245 and 290 ps at a supply voltage of 4.5 and 4 V, respectively. These values are about 1.4-1.2 times better than the 0.8- mu m BiCMOS gate operating at 5 V. A power dissipation of 0.4 mW was obtained with a 0.93-pF load, 4-V supply voltage, and 140-MHz operation. The power dissipation is comparable to that of a CMOS gate. >

An 8 ns 256 K BiCMOS RAM

A 256 K word*1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150 mW at standby mode, is presented. To achieve an address access time of less than 10 nss and high packing density, an advanced 1.0 mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is used. A 9 GHz bipolar transistor cutoff frequency, 0.26 ns ECL gate propagation delay time, and 0.35 ns BiCMOS gate have been obtained. A 1.0 mu m design rule permits layout of an NMOS memory cell with a high-resistance polysilicon load in 54.7 mu m/sup 2/ and a 4.09*8.60 mm/sup 2/ chip. High performance is achieved by an optimized circuit design using a new input buffer, a BiCMOS decoder, and a high-speed bipolar sense amplifier. An active pull-down emitter-follower circuit and a BiCMOS current mirror ECL-MOS level shift circuit improve input buffer delay to less than 1.8 ns. A power-down technique has been studied to reduce standby power. Some experimental results are presented. High-speed address access is observed over a wide operational range. >