BiCMOS Drivers Research Articles

High-Speed Ultralow-Power Hybrid Optical Transmitter Module With InP I/Q-SEMZM and BiCMOS Drivers With 4-b Integrated DAC

A hybrid optical transmitter module comprising a 15-segment InP in-phase/quadrature-phase segmented Mach–Zehnder modulator and two SiGe:C BiCMOS drivers featuring integrated 4-b digital-to-analog converter functionality is described. The drivers, fabricated in the 0.13- $\mu \text{m}$ process of IHP, deliver a differential output voltage of $2.5~V_{\mathrm{ pp}}$ across all the 15 segments while dissipating less than 1 W of power each, at the maximum. Clear electrical eye diagrams up to 40-Gb/s from every output are reported. The module allows a wide range of modulation formats, among which up to eight-pulse amplitude modulation and polarization-division-multiplexed (PDM) 64-quadrature amplitude modulation (QAM) back-to-back error-free electro-optical transmission at a record speed of 32 GBd are demonstrated. The 32-GBd PDM 64-QAM signal was transmitted error-free over 80 km of standard single-mode fiber, featuring 7.8-pJ/b energy consumption. The devised hybrid arrangement proves the suitability of SiGe HBT drivers for achieving higher speeds over their CMOS counterparts, with comparable low power dissipation, for advanced optical transceivers.

Comments on "Area-time optimal adder design"

A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompson, is incorrect. With suitable corrections, a correct 32-bit fast carry generator design is then presented. Next, BiCMOS technology is applied to implement the subcircuit of fast carry generator to accelerate the critical path. The authors show that the critical path delay of 16-bit, 32-bit and 66-bit adders is respectively shortened to 83.89%, 86.89% and 90.62% after introducing the BiCMOS drivers. >

Substrate current reduction techniques for BiCMOS DRAM

Substrate current (I/sub BB/) reduction techniques useful to BiCMOS DRAM's are proposed through a comparison of the I/sub BB/ characteristics for a BiCMOS driver and a CMOS driver and through a clarification of the I/sub BB/ generation mechanism. Four key results are obtained. One is that the I/sub BB/ of conventional BiCMOS drivers is unacceptably high, i.e, three times larger than that of CMOS drivers. Another is that the excessive I/sub BB/ of BiCMOS drivers is generated by the saturation of bipolar transistors, which results from a collector voltage decrease caused by large amounts of collector current flowing through the collector saturation resistance r/sub cs/. The third result concerns proposals for I/sub BB/ reduction techniques. One features two collector outputs terminals for avoiding the r/sub cs/ effect and the other features application of a low supply voltage for the base. The last result is that BiCMOS drivers using the I/sub BB/ reduction techniques make it possible to achieve 1-Mbit BiCMOS DRAM'S with I/sub BB/ levels comparable to those of conventional CMOS DRAM's. >

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8- mu m BiCMOS and triple-layer metallization technology, has an area of 5.87 mm*5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW. >