BiCMOS Buffer Research Articles

CMOS PWM CONTROL CIRCUIT WITH PROGRAMMABLE DEAD TIME

Some types of dc–dc power converters require a control circuit to produce two pulse width modulated (PWM) signals that are 180° out of phase. In many applications, a critical element of the control circuit is the capability to program a specified amount of dead time when both PWM signals are low. This paper presents an integrated circuit implementation of a control circuit that can be programmed with digital inputs to produce variable dead times. The circuit was fabricated in 2-micron CMOS technology with a 1.7 mm × 1.7 mm die and tested to verify complete functionality. Control chips that are currently available require external capacitor/resistor combinations to produce the required dead time. A unique design of a Bi-CMOS buffer with an output current up to 1.4 A is also included, which enables the PWM circuit to directly drive the gates of power MOSFETs.

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B/spl radic/F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 /spl mu/m, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e/sup 2.3/(/spl ap/10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e/sup 1.6/(/spl ap/5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants. >

Design and optimization of buffer chains and logic circuits in a BiCMOS environment

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied. >

An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits

A scheme for optimizing the overall delay of BiCMOS driver circuits is proposed in this paper. Using this optimization scheme, it is found that the delay is minimized when the maximum collector current of the bipolar transistors is equal to the onset of high current effects. Using this assumption, an accurate BiCMOS delay expression is derived in terms of the bipolar and MOS device parameters. The critical device parameters are then identified and their influence on the circuit speed discussed. An overall circuit delay expression for optimizing BiCMOS buffers is derived and a comparison made with CMOS buffers. It is shown that BiCMOS circuits have a speed advantage of 1.7 or an area advantage of about 5 for 2- mu m feature sizes. In order to predict the future performance of BiCMOS circuits, a figure of merit is derived from the delay expression. Using the figure-of-merit expression, it is seen that future BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicrometer dimensions under constant load capacitance assumption. >

Analysis and optimization of BiCMOS digital circuit structures

Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS/CML (coupled-mode logic), and ECL (emitter-coupled logic)/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors involved in designing such circuits are discussed. The derived delay expressions can also be used in CAD tools for optimizing BiCMOS circuits and systems. >

Scaling of digital BiCMOS circuits

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling. >