Bias Temperature Instability Research Articles

Real-Time Monitoring Method and Circuit Based on Built-In Reliability Prediction.

The failure of different chips under working conditions is influenced by various stress states such as different voltages, temperatures, stress durations, and stress variations. Therefore, the failure time has a great degree of dispersion, and similar chips may exhibit different failure mechanisms due to variations in their working environments. This paper proposes three system-on-chip reliability failure prediction unit circuits: the time-dependent dielectric breakdown prediction circuit, the negative bias temperature instability prediction circuit, and the hot carrier injection prediction circuit. These circuits are embedded within the main chip, enabling real-time failure prediction and reliability mechanism diagnosis in the same working environment as the main chip. The three reliability failure prediction circuits are compact and energy efficient, allowing for their integration into a system on a chip as IP cores that provide early warning signals before system-on-chip failure. Compared to traditional reliability prediction methods, this approach offers the advantages of accurately identifying failure mechanisms, predicting failure times, and enabling real-time online monitoring.

Recovery of Quasi-Permanent Bias Temperature Instability in SiC MOSFETs and Its Physical Mechanism

Recovery of Quasi-Permanent Bias Temperature Instability in SiC MOSFETs and Its Physical Mechanism

Gate Length Dependence of Bias Temperature Instabilities up to 400 °C in 4H-SiC CMOS Devices

Gate Length Dependence of Bias Temperature Instabilities up to 400 °C in 4H-SiC CMOS Devices

Low-pressure oxidation for improving interface properties and voltage instability of SiO2/4H-SiC MOS capacitor

The impact of high-temperature sub-atmospheric oxidation pressure on the interface properties of n-type 4H-SiC metal–oxide–semiconductor capacitors has been systematically investigated in this report. The bias temperature instability measurement was used to calculate the mobile ions and near-interface trap density that led to device instability at high temperatures. The density of near interface traps decreased from 88.3 × 1011 cm−2 to 10.2 × 1011 cm−2 when the growth pressure of SiO2 was reduced from 1 atm to 0.1 atm, while the mobile ions density decreased from 83.5 × 1011 to 4.18 × 1011 cm−2. The results show that SiO2 growing under lower oxidation pressure has better interfacial quality. The underlying mechanism was explored by secondary ion mass spectrometry (SIMS) and x-ray photoelectron spectroscopy (XPS). It is speculated that the SiO2/SiC interface was reconstructed under low-pressure oxidation: the excess Si-related defects near the interface, such as SiOxCy, were released while O atoms were accumulated to promote a complete oxidation reaction, thereby effectively reducing the number of defects in the SiO2 film and improving device performance.

Exploring the Impact of Negative Bias Temperature Instability in SiGe p-MOSFETs Utilizing a Two-Stage Model

Exploring the Impact of Negative Bias Temperature Instability in SiGe p-MOSFETs Utilizing a Two-Stage Model

Investigation and Improvement of the Bias Temperature Instability in Carbon Nanotube Transistors

Investigation and Improvement of the Bias Temperature Instability in Carbon Nanotube Transistors

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

Charge trapping gate stack enabled non-recessed normally off AlGaN/GaN HEMT with high threshold voltage stability

This paper reports a non-recessed normally off AlGaN/GaN high-electron-mobility transistor (HEMT) with a charge trapping gate dielectric stack. The charge trapping gate dielectric stack featuring a low density of fixed positive charges consists of an O3-based Al2O3 tunneling layer and an O3-based HfO2 blocking layer, both deposited via atomic layer deposition. For HEMT with a 15 nm AlGaN barrier layer, a threshold voltage of 2.57 V and an on-resistance of 8.50 Ω × mm are achieved. For positive bias temperature instability (PBTI) testing, the electric field provided by the 15 nm AlGaN layer serves as a barrier to channel carriers, significantly enhancing the PBTI test stability. The optimized gate dielectric stack enables the fabrication of the non-recessed normally off metal–insulator–semiconductor-HEMT with enhanced threshold voltage (Vth) stability.

Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction

As CMOS technology continues to scale down, the aging effect—known as negative bias temperature instability (NBTI)—has become increasingly prominent, gradually emerging as a key factor affecting device reliability. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. However, traditional aging-aware timing analysis methods, typically based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations or aging-aware timing libraries, struggle to balance prediction accuracy with computational cost. In this paper, we propose a multi-view graph learning framework for path-level aging-aware timing prediction, which combines the strengths of the spatial–temporal Transformer network (STTN) and graph attention network (GAT) models to extract the aging timing features of paths from both timing-sensitive and workload-sensitive perspectives. Experimental results demonstrate that our proposed framework achieves an average MAPE score of 3.96% and reduces the average MAPE by 5.8 times compared to FFNN and 2.2 times compared to PNA, while maintaining acceptable increases in processing time.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Analyzing Aging Effects on SRAM PUFs: Implications for Security and Reliability

The aging effects on Static Random-Access Memory Physical Unclonable Functions (SRAM PUFs) pose significant security and reliability challenges for current hardware systems. SRAM PUFs utilize process variations in integrated circuits for secure key generation and device authentication. However, aging effects such as bias temperature instability (BTI) and hot carrier injection (HCI) may change SRAM cell characteristics and affect PUF responses. This study addresses various aging-induced variation challenges, identifies security vulnerabilities, and provides innovative approaches to risk reduction. Furthermore, this study focuses on concerns about SRAM PUF reliability. In this regard, mitigation approaches like adaptive reconfiguration, error correction codes, and multi-modal PUFs are introduced to enhance the resilience of SRAM PUFs. This study concludes by outlining future research directions and prospects for improving SRAM PUF-based security solutions by several orders of magnitude. This is carried out with various complexities related to semiconductor device aging.

Study on reliability improvement for p-type FeFinFET under negative-bias temperature instability stress with appropriate fluorine plasma treatment

This study investigates the effects of fluorine plasma treatment (FPT) on the reliability of p-type ferroelectric fin-shaped field-effect transistors (FeFinFETs) based on Hf0.5Zr0.5O2 (HZO) and subjected to negative bias temperature instability (NBTI). Compared with non-FPT devices, FeFinFETs treated with FPT exhibited higher drive currents and mobility for fresh devices, indicating an improvement in interface quality. After NBTI stress, FPT devices exhibited lesser threshold voltage shift and subthreshold swing degradation than non-FPT devices, which is attributed to the passivation of dangling bonds between the Si/HZO interfaces by fluorine. Si–F bonds are less susceptible to breakage than Si–H bonds. These findings suggest that FPT is a promising technique to enhance the reliability and performance of FeFinFETs based on Hf0.5Zr0.5O2.

Positive Bias Temperature Instability in SiC-Based Power MOSFETs.

This paper investigates the threshold voltage shift (ΔVTH) induced by positive bias temperature instability (PBTI) in silicon carbide (SiC) power MOSFETs. By analyzing ΔVTH under various gate stress voltages (VGstress) at 150 °C, distinct mechanisms are revealed: (i) trapping in the interface and/or border pre-existing defects and (ii) the creation of oxide defects and/or trapping in spatially deeper oxide states with an activation energy of ~80 meV. Notably, the adoption of different characterization methods highlights the distinct roles of these mechanisms. Moreover, the study demonstrates consistent behavior in permanent ΔVTH degradation across VGstress levels using a power law model. Overall, these findings deepen the understanding of PBTI in SiC MOSFETs, providing insights for reliability optimization.

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

An investigation into the thermal surface contact resistance, fin width and temperature on negative bias temperature instability during self-heating

This work investigates the impacts of the thermal surface contact resistance (SR), fin width and temperature on the negative bias temperature instability (NBTI) during self-heating based on 14 nm p-FinFET through technology computer-aided design (TCAD) tool. In order to promote the accuracy of simulation, the experimental data are used to calibrate the TCAD results. The simulation results reveal that as SR increases, the lattice temperature rises by 20.07 %, which leads to a 15.84 % decrease of the carrier mobility and finally a reduction of the saturation current by 5.07 %. Moreover, as WFin decreases from 8 nm to 2 nm, the device threshold voltage increases by 15.41 %, resulting in that the saturation current reduces by 19.06 %. Besides, with an increase of the ambient temperature from 300 K to 500 K, the lattice temperature and trapped charge rise by 60.48 % and 12.53 %, respectively, which eventually leads to an 18.13 % decrease of the saturation current.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130◦C and T = 25◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130◦C) compared to lower operating temperatures (T = 25◦C).