Bias Generator Research Articles

Manipulation of perpendicular exchange bias and spin-orbit torques via MgO in Pt/Co/MgO films

We study the perpendicular exchange bias (PEB) and spin-orbit torque (SOT) generation in the Pt/Co/MgO heterostructure by changing the thickness of the MgO layer. We show that the oxidation of the beneath Co layer increases with the MgO thickness. Strong PEB is obtained in the Pt/Co/MgO films, which exhibits a much higher blocking temperature compared with that in the Pt/Co/CoO films. Furthermore, it is found that the MgO thickness has significant effect on the SOT generation. Maximum values of the SOTs are obtained with a 0.8 nm-thick MgO layer, which decreases by increasing the MgO thickness from 0.8 to 1.6 nm. Our results shed a light on the essential role of the MgO layer in the heavy metal/ferromagnet/MgO heterostructure, a typical material system in spintronic devices, and provide a way to manipulate the magnetic properties and the SOTs by oxide layers.

Learning Vertex Representations for Bipartite Networks

Recent years have witnessed a widespread increase of interest in network representation learning (NRL). By far most research efforts have focused on NRL for homogeneous networks like social networks where vertices are of the same type, or heterogeneous networks like knowledge graphs where vertices (and/or edges) are of different types. There has been relatively little research dedicated to NRL for bipartite networks. Arguably, generic network embedding methods like node2vec and LINE can also be applied to learn vertex embeddings for bipartite networks by ignoring the vertex type information. However, these methods are suboptimal in doing so, since real-world bipartite networks concern the relationship between two types of entities, which usually exhibit different properties and patterns from other types of network data. For example, E-Commerce recommender systems need to capture the collaborative filtering patterns between customers and products, and search engines need to consider the matching signals between queries and webpages. This work addresses the research gap of learning vertex representations for bipartite networks. We present a new solution BiNE, short for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bi</b> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">partite</i> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</b> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">etwork</i> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</b> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mbedding</i> , which accounts for two special properties of bipartite networks: long-tail distribution of vertex degrees and implicit connectivity relations between vertices of the same type. Technically speaking, we make three contributions: (1) We design a biased random walk generator to generate vertex sequences that preserve the long-tail distribution of vertices; (2) We propose a new optimization framework by simultaneously modeling the explicit relations (i.e., observed links) and implicit relations (i.e., unobserved but transitive links); (3) We explore the theoretical foundations of BiNE to shed light on how it works, proving that BiNE can be interpreted as factorizing multiple matrices. We perform extensive experiments on five real datasets covering the tasks of link prediction (classification) and recommendation (ranking), empirically verifying the effectiveness and rationality of BiNE. Our experiment codes are available at: <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/clhchtcjj/BiNE</uri> .

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI

The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected by environmental temperature and process variations. Mitigating the effect of these phenomena becomes crucial when these devices operate near-threshold, due to the magnification of process variations and to the strong temperature inversion effect that affects advanced technology nodes in low-voltage corners, which causes huge overhead due to margining for timing closure. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to maximize energy efficiency at run-time exploiting body biasing on a ULP platform operating near-threshold. The proposed method relies on on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with an on-chip low-power body bias generator. We correlate the measurement performed by the PMBs to the maximum achievable frequency of the system, deriving a predictive model able to estimate it with an error of 9.7% at 0.7 V. To minimize the effect of process variations we propose a calibration procedure that allows to use a PMB model affected by only the temperature-induced error, which reduces the frequency estimation error by 2.4x (from 9.7% to 4%). We finally propose a controller architecture relying on the derived models to automatically regulate at run-time the body bias voltage. We demonstrate that adjusting the body bias voltage against environmental temperature variations leads up to 2X reduction in the leakage power and a 15% improvement on the global energy consumption when the system operates at 0.7 V and 170 MHz.

A 373-F² 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and VSS Bias-Based Dark-Bit Detection

This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement–enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated ${V}_{\text {SS}}$ -bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 °C, which is 14 $\times $ better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits $\times $ 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and −40 °C to 120 °C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800–22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F 2.

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 μW and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V.

Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing

This article presents a fully integrated, wide linear dynamic range (DR) optical sensor array combining linear and single-photon avalanche diode (SPAD) operation within each pixel. A pulse-counting readout scheme provides in-pixel digitization in an area-efficient manner for both the operation modes, enabling fully parallel measurement across the array. The proposed dual-mode optical sensor array alternately requires high-voltage (10–20 V) and low-voltage supply (2–5 V) for reverse bias of the photodiodes, which is provided by a reconfigurable, closed-loop high-voltage charge pump in the same substrate. An $8\times 8$ array architecture along with the dual-mode bias generator is fabricated in a general purpose 180-nm CMOS process and demonstrates 129-dB DR while maintaining linear photoresponse operating with a dual-mode frame rate of 20 Hz. We present a pixel design methodology for implementing a dual-mode optical sensor scalable to an array format, as well as high-voltage dc–dc conversion in a low-voltage CMOS process.

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc-dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from -20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

Effects of biased hypothesis generation on self-directed category learning.

Psychologists and educators have long pointed to myriad benefits of self-directed learning. Yet evidence of its efficacy in real-world domains is mixed and it remains unclear how it is constrained by basic perceptual and cognitive processes. Previous work suggests that, in particular, self-directed learning is affected by the way that people generate hypotheses as they learn. This study examines how biased hypothesis generation affects the learning of categorical rules, a basic building block of concept learning, through self-directed selection of training data. In both perceptual and abstract category learning tasks, participants' hypotheses regarding an unknown classification boundary were influenced by how features were represented. This bias had persistent effects on their ability to learn the underlying categorical relationship despite their opportunity to control the selection of training items. The results demonstrate that self-directed control can be beneficial for both perceptual and abstract category learning, but that the ability to discover rules of a particular form depends on how the learning environment guides the generation of new hypotheses. (PsycINFO Database Record (c) 2019 APA, all rights reserved).

High Performance Robust Keeper Design Technique for Wide Fan-In Domino OR Logic Using CNTFET 16nm Node Technology

This paper deals with the proposed adaptable threshold keeper&amp;dynamic buffer technique(ATKDB) for CNTFET based wide fan in domino OR logic which simultaneously reduces the average power and propagation delay of the wide fan in logic implementationcompared to various dominogatetopologies.The proposed technique provides adaptable threshold voltage for the keeper transistor by means of a designed body bias generator which drives thebulk of the keeper and there by regulates the power. The design also includes a dynamic buffer at the output node to reduce pre-charge phase power consumption. With this technique, threshold voltage for keeper device is varied dynamically to reduce the contention current and clock loading. The proposed system was tested for 16 and 32 input domino gate using 16nm CNTFET model andthesatisfactoryresults w.r.t power and delay wereobtained.

A Design Method of a Cell-Based Amplifier for Body Bias Generation

A Design Method of a Cell-Based Amplifier for Body Bias Generation

Design of a 0.20–0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications

This paper presents a 10-bit SAR ADC operating at a supply voltage (VDD) from 0.200 to 0.250 V. In the proposed ADC structure, the positive input of the comparator is fixed at VDD to bias the comparator’s input transistor pair with a sufficient gate-to-source voltage at such a low VDD. We propose an ultra-low VDD temperature-compensated bias generator to bias the comparator for addressing the severe temperature-dependent issue of the MOSFETs in the comparator, which operate in the deep subthreshold region. Detailed circuit analysis and derivation of design requirements are presented. A double-boosted and low-leakage sampling switch is also proposed to alleviate the severe leakage issue at low sampling rates. A test chip has been designed and fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm2. Measurement results show that the ADC achieves stable performance in the VDD range. At 0.225 V, the DNL and INL are within +1.04/−0.66 and +0.97/−1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR at the Nyquist input frequency is 49.2 dB at 450 S/s. The whole ADC totally consumes 0.85 nW at 0.225 V including circuit leakages. The sub-nW power consumption makes it well suited for self-sustainable Internet-of-Things applications.

DC magnetic bias suppression strategy for series transformers in dynamic voltage restorers

In actual engineering, the dynamic voltage restorer is mainly used to protect the load from the voltage drop of the grid, and is inserted between the grid and the load through the series transformer. The dynamic voltage restorer (DVR) can easily cause DC bias and generate magnetizing inrush current at the beginning of compensation voltage drop. This is also a common problem in DVR engineering applications. The usual way to solve this problem is to design the transformer core to twice the rating, but this will greatly increase the size and cost of the transformer. In order to ensure the safe, reliable and stable operation of the DVR and reduce the cost and volume of the transformer, it is necessary to suppress DC bias of the transformer. Based on the principle analysis of the DC bias generation in series transformers, a DC bias suppression strategy was proposed to control the amplitude of the first half of the output voltage of the DVR. The DVR system model was built in Simplorer, Matlab and Maxwell for co-simulation, and the effects before and after the DC bias suppression strategy were compared.

Fully-Integrated Charge Pump Design Optimization for Above-Breakdown Biasing of Single-Photon Avalanche Diodes in 0.13-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS

A design methodology for an area-optimized integrated charge pump is described suitable for on-chip high-voltage reverse bias of single-photon avalanche diodes (SPADs). The high-voltage generation block is implemented in a general-purpose 0.13- $\mu \text{m}$ CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON–OFF regulation scheme with dynamic charging and discharging capability of the charge pump provides fast recovery of the output bias voltage during SPAD transients, where overshoot and undershoot must both be corrected during active quench and reset. Following a SPAD avalanche current pulse, the measured transient recovery time is 500 ns from a 150-mV overshoot and a 500-mV undershoot to reach 99% of steady-state output. The implemented SPAD bias generation system occupies 0.175-mm2 chip area, without requiring an off-chip load capacitor.

FDSOI-Based Area and Power-Efficient Robust Negative Charge Pump for Localized Body Bias Generator

This work exhibits an area-efficient negative charge pump (NCP) solution for an on-chip localized body bias generator (BBG) which has almost zero settling time for use in critical path replicas clearance. Also, the proposed circuit incorporates process and voltage compensation and dynamic energy optimization. Its temperature variation trend is regular and justified. The negative charge pump is implemented using Cadence Virtuoso for design and Eldo for simulation with 28-nm ultra thin body and box—fully depleted silicon on insulator (UTBB-FDSOI) for 0.85–1.3 V inputs. The implemented design is single-stage design, so it is area efficient. Its area occupancy is 2.94 µm2 and power occupancy is 34 µW. Negative charge pump-based body bias generator can be sprinkled with standard cells to enhance performance and robustness of the design.

Flood Forecasting Based on an Improved Extreme Learning Machine Model Combined with the Backtracking Search Optimization Algorithm

Flood forecasting plays an important role in flood control and water resources management. Recently, the data-driven models with a simpler model structure and lower data requirement attract much more attentions. An extreme learning machine (ELM) method, as a typical data-driven method, with the advantages of a faster learning process and stronger generalization ability, has been taken as an effective tool for flood forecasting. However, an ELM model may suffer from local minima in some cases because of its random generation of input weights and hidden layer biases, which results in uncertainties in the flood forecasting model. Therefore, we proposed an improved ELM model for short-term flood forecasting, in which an emerging dual population-based algorithm, named backtracking search algorithm (BSA), was applied to optimize the parameters of ELM. Thus, the proposed method is called ELM-BSA. The upper Yangtze River was selected as a case study. Several performance indexes were used to evaluate the efficiency of the proposed ELM-BSA model. Then the proposed model was compared with the currently used general regression neural network (GRNN) and ELM models. Results show that the ELM-BSA can always provide better results than the GRNN and ELM models in both the training and testing periods. All these results suggest that the proposed ELM-BSA model is a promising alternative technique for flood forecasting.

A 2.0 GHz IQ Imbalance Compensator With Programmable Switch Biases in a Passive Mixer

This brief presents a frequency-independent IQ imbalance compensator with low complexity. The proposed compensator is a revised AND-Type passive mixer with eight programmable switch bias generators. The quadrature phase and gain compensation are simultaneously generated by programming these bias voltages. The generated quadrature compensation is approximately first-order linear to the differential and common mode variances of these bias voltages. The compensator is fabricated within a 2.0 GHz direct-conversion transmitter in a 0.13 μm RFCMOS process. The measured image reject ratio adjustment range is 34.8-60.4 dB. All eight 7-step (3-bit D/A converter) bias generators dissipate 1.0 mA at 1.35 V supply.

A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm

This brief presents a low-power forward and reverse body bias (FRBB) generator with body bias (BB) switches to dynamically set BB voltage. The reverse BB (RBB) P-well generator uses pulse frequency modulation (PFM)-based switching capacitor power converter to achieve low power consumption in a wide load current range of 1–30 $\mu ~\text{A}$ . The FBB adopts class-AB output stage and an over-current indicator to detect large body diode forward conduction leakage current. BB switch is introduced to dynamically configure the FRBB generated voltage. The proposed FRBB with BB switch is fabricated in a CMOS 40-nm triple well process, occupying an area of around 0.1 mm2. The 300k digital gates are used as the load for test. The measured active current for FBB and RBB are 13 and $5~\mu \text{A}$ , respectively.

Scanning of speechless comics changes spatial biases in mental model construction.

The mental representation of both time and number shows lateral spatial biases, which can be affected by habitual reading and writing direction. However, this effect is in place before children begin to read. One potential early cause is the experiences of looking at picture books together with a carer, as those images also follow the directionality of the script. What is the underlying mechanism for this effect? In the present study, we test the possibility that such experiences induce spatial biases in mental model construction, a mechanism which is a good candidate to induce the biases observed with numbers and times. We presented a speechless comic in either standard (left-to-right) or mirror-reversed (right-to-left) form to adult Spanish participants. We then asked them to draw the scene depicted by sentences like 'the square is between the cross and the circle'. The position of the lateral objects in these drawings reveals the spatial biases at work when building mental models in working memory. Under conditions of highly consistent directionality, the mirror comic changed pre-existing lateral biases. Processes of mental model construction in working memory stand as a potential mechanism for the generation of spatial biases for time and number.This article is part of the theme issue 'Varieties of abstract concepts: development, use and representation in the brain'.

A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process

A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm2 active area.

Atrophied thymus produces altered repertoire of tTregs with potential to break the balance of peripheral tolerance

Abstract We have previously shown that in the age-related atrophied thymus, there is an increased ratio of thymic T regulatory (tTreg) cells to thymic T conventional (tTcon) cells, suggesting that the aged thymus has an enhanced tTreg generation. It is also known that in the periphery of aged mice and humans, there is an accumulation of peripheral Tregs. We raise the following question: why is the increased Treg population unable to suppress self-reactivity in the elderly? We utilized a sub-lethally irradiated chimeric mouse model in which OT-II TCR transgenic bone-marrow cells were transplanted into RIP-mOVA host mice. Therefore, OVA serves as a mock self-antigen, and because this transgene is driven by the rat insulin promotor, the pancreas of these mice expresses OVA. Further, the mOVA mice also carry a FoxN1-floxed gene, which can be conditionally knocked-out via CreERT transgene activation by injection(s) with tamoxifen to induce thymic atrophy. We observed that chimera mice with induced thymic atrophy show total Tregs (termed pan-Tregs) were increased but OT-II specific Tregs were slightly decreased in the spleen. Additionally, there is a dramatic decrease in the OTII-specific Tregs found in the pancreas, and pancreatic atrophy was observed in these mice compared to those with normal thymus. Our initial results suggest that thymic atrophy leads to a biased tTreg generation that manifests in decreased selftissue specific-Tregs. Therefore, although pan-Tregs may accumulate and be enhanced with age, tissue-specific peripheral tolerance may be poised to fail.