Biquad Cells Research Articles

Boosting the Quality Factor of the Shadow Bandpass Filter

This paper proposes a new method to increase the quality factor of the shadow bandpass filter. The proposed circuit topology is simple, with the use of conventional biquad cell along with external amplifiers. The major advantageous feature is that the quality factor of the filter is boosted up whereas the gain of the external amplifier is significantly reduced. Moreover, the presented idea can be applied to the shadow filter in both current and voltage modes. The proposed scheme is justified via circuit performance. The performance is compared with the previous research works in the same arena. The results show that a feedback signal and a properly chosen gain incredibly boost up the quality factor of the shadow bandpass filter. Simulations by PSpice using 0.18-[Formula: see text]m CMOS-level parameters confirm the validity of the proposed work.

A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differen...

A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers

A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.

A 264 MHz CMOS Gm—C LPF for ultra-wideband standard

A 264 MHz CMOS 4th Gm—C LPF target for the UWB standard is presented. The filter is designed by cascading two biquad cells. Compared with the previously published biquad cells, the biquad proposed here saves 1 transconductor, 3 CMFB networks and 2 capacitors. Benefiting from these merits, the power consumption and chip area of the 4th order UWB LPF are reduced dramatically without other characteristics being affected. The LPF is designed and fabricated with TSMC 0.18 μm 1P6M CMOS technology. The implemented LPF achieves a power gain of −0.5 dB. The measured frequency response matches well with that of the simulating results. The core chip area is only 0.06 mm2, which has a wonderful advantage over those from similar work. The LPF excluding test-buffers dissipates a total current of 3 mA from the 1.8 V power supply.

Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping

A novel class of filters (called pipe filters) that features in-band noise reduction is presented and a current mode biquad cell based on cross-connected cascoded devices is introduced. The presented solution gives in-band high-pass noise shaping and passive pre-filtering of out-of-band blockers. This results in both low in-band noise and high out-of-band IIP3. A 4th-order lowpass prototype in 90 nm CMOS for WCDMA application features 32 μW in-band noise (when integrated over the 2 MHz bandwidth as defined by the standard) and +36 dBm out-of-band IIP3 which results in a 75 dB SFDR with 1.25 mW power consumption. Active die area is 0.5 mm2.

Mixed-integrator-based bi-quad cell for designing a continuous time filter

A new mixed-integrator-based bi-quad cell is proposed. An alternative synthesis mechanism of complex poles is proposed compared with source-follower-based bi-quad cells which is designed applying the positive feedback technique. Using the negative feedback technique to combine different integrators, the proposed bi-quad cell synthesizes complex poles for designing a continuous time filter. It exhibits various advantages including compact topology, high gain, no parasitic pole, no CMFB circuit, and high capability. The fourth-order Butterworth lowpass filter using the proposed cells has been fabricated in 0.18 μm CMOS technology. The active area occupied by the filter with test buffer is only 200 × 170 μm2. The proposed filter consumes a low power of 201 μW and achieves a 68.5 dB dynamic range.

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band <formula> <tex>$G_m$</tex></formula>–<formula><tex>$C$</tex></formula> Filters

A 330-MHz fifth-order G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C continuous-time low-pass filter with 24-dB boost is presented. Existing solutions are found to be unsuitable for low-power, wide-band, and high-boost operation. The proposed solution realizes two symmetric real axis zeros by efficiently combining transfer functions associated with all nodes of cascaded biquad cells. Application of Gilbert cell as a variable transconductor, for achieving constant parasitic capacitance across wide programmability range, is illustrated. A new common-mode feedback error amplifier that improves common-mode accuracy without compromising on bandwidth or circuit complexity is introduced. A prototype is fabricated in a standard 0.35-mum CMOS process. Experimental results show -41 dB of IM3 for 250-mV peak-peak swing with 43 mW of power dissipation

A 4th-Order Active-&lt;tex&gt;$G_m$&lt;/tex&gt;-RC Reconfigurable (UMTS/WLAN) Filter

A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses the cascade of two Active-Gm-RC biquad cells. A single opamp is used for each biquad and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced w.r.t. other closed-loop filter configurations. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13 mum CMOS technology occupies a 0.9 mm2 area and it consumes 3.4 mW and 11 4.2 mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance

Compact high-frequency low-power continous-time gm-C biquad cell

A low-power CMOS continuous-time biquad cell is presented. The cell presents a compact structure, in which only one current branch for each side of the differential structure is present. In addition the filter exhibits other characteristics which allows reduced power consumption because of the absence of parasitic poles and CMFB circuit.

A high-selectivity switched-capacitor bandpass filter

A high-selectivity switched-capacitor bandpass filter is presented. The filter center frequency is 100 kHz with a -3 dB bandwidth of 980 Hz (i.e., with a quality factor Q/spl sim/100). This has been implemented with a 12th-order transfer function whose poles are placed at only two frequencies. This choice has been used in the integrated circuit realization. In fact, the transfer function has been implemented using the cascade of six biquad cells of only two types. For the available 20 samples, the center frequency mean-value error is lower than 0.2%, and the Q mean-value error is lower than 0.2% as well. The filter is realized in a not-recent BiCMOS technology (L/sub NMOS/=4 /spl mu/m, L/sub PMOS/=3 /spl mu/m). The same performance (opamp, switches, and overall filter) can be easily obtained with a standard scaled-down (0.35 /spl mu/m, for instance) CMOS technology. In this direction, an evaluation of the area and power consumption of the circuit as implemented in a standard 0.35-/spl mu/m CMOS technology is finally given.