Behavioral Synthesis System Research Articles

A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique

This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED) technique. In REcomputing with Shifted Operands (RESO), operations (additions, subtractions, etc.) are carried out twice-once on the basic input and once on the shifted input. Results from these two operations are compared to detect an error. Although using RESO operators in RT-level designs is straightforward, it entails time and area overhead. In contrast, ARESO does not use specialized RESO operators. In ARESO, an algorithm is carried out twice-once on the basic input and once on the shifted input. Results from these two algorithm-level instantiations are compared to detect an error. By operating at the algorithm level, ARESO exploits RT-level scheduling, pipelining, operator chaining, and multicycling to incorporate user-specified error detection latencies. ARESO supports hardware versus performance versus error detection latency tradeoffs. The authors validated ARESO on practical design examples using the Synopsys Behavior Compiler (BC). An industry standard behavioral synthesis system.

Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Concern over power dissipation, coupled with the continuing rise in system size and complexity, means that there is a growing need for high-level design tools capable of doubt automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described here features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via SPICE simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included, encompassing: supply voltage scaling, clock gating, input latching, input gating, low-power cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs.

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

Microarchitectural synthesis for rapid BIST testing

The impact of testability on design cost necessitates its consideration during the earliest stages of synthesis. Built-in self test (BIST) is an accepted testing approach, but its application to many designs is limited by the long test application time required to achieve high fault coverage. This work addresses the problem of BIST test time for high fault coverage by targeting test concurrency during high-level and structural synthesis. High-level synthesis generates RTL circuits which guarantee concurrent controllability and observability of all hardware components from test registers. Structural synthesis for testability completes the microarchitectural definition by specifying the test registers in the circuit, and defining a BIST test plan for the circuit. Remaining test conflicts are avoided without reducing test throughput by using partial-intrusion BIST to enable test data to be pipelined through nontest registers. The use of pipelined BIST testing in conjunction with high-level synthesis for test conflict minimization enables reduced test time through high test concurrency. Partial-intrusion BIST reduces the number of test registers by using nontest registers to propagate test data. Both behavioral and structural synthesis are directed by testability metrics which measure the test concurrency of a design. The use of these metrics in an integrated behavioral synthesis system pioneers the inclusion of test concurrency issues in microarchitectural synthesis. Experimental results using this synthesis system, SYNCBIST, show that designs generated by this approach are testable with few patterns, and using few test registers.

On-line testing of statically and dynamically scheduled synthesized systems

Most digital systems at some time during use have areas (modules) that are "dead" in the sense that they do not contain valid data, i.e., the data that was processed or generated by that area has been passed on to a subsequent stage and will not be required (read) again. In a synthesized system, where the flow of data is determined explicitly by an on-chip (synthesized) controller, the question of which areas will be dead or not (and when) is known in advance. There are areas and times when the "use" is data-dependent, but then the use is known to the controller at that time. This deadtime can be exploited to run a test pattern (either complete or in part) through the unused area, thereby giving the ability to continuously monitor the "health" of the overall system with very little (sometimes zero) impact on the processing capability. This has obvious applications in situations where reliability is a concern. There exist systems where an area is so heavily used that it is impossible to perform any testing at a serious rate; in this case the area may either be partially tested (or tested at a lower rate) or the processing of "reap" data periodically halted to anew a more thorough test to take place with concomitant throughput degradation. This paper describes a behavioral synthesis system that can detect and exploit dead areas for automatic testing. Pertinent aspects of the controller are described, and a number of dead area statistics (including "test throughput") generated from real designs are reported.

An optimal clock period selection method based on slack minimization criteria

An important decision in synthesizing a hardware implementation from a behavioral description is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of clock period could result in operations being idle for a large portion of the clock period and, consequently, affect the performance of the synthesized design. In this article, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.

Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan

We introduce BETS, a behavioral test synthesis system, for the synthesis of high-throughput, area-efficient testable designs. While hardware sharing is a powerful technique to achieve area efficiency, it may adversely affect the testability of the synthesized design by introducing new loops. Besides CDFG loops, hardware sharing introduces three other types of loops: assignment loops, sequential false loops, and register files cliques. We provide a comprehensive analysis and a formal grammar characterization of the sources of loops in the data path during behavioral synthesis. Partial scan is a cost-effective technique for sequential circuit testing. Hardware sharing of scan registers can be used to minimize the number of scan registers required to synthesize data paths with minimal number of loops. The scan registers can be shared amongst several variables of the CDFG, to break not only the loops in the CDFG, but also the very loops introduced in the data path by hardware sharing. A new random walk based algorithm is proposed to break all CDFG loops using a minimal number of scan registers. The subsequent scheduling and assignment phase avoids formation of loops in the data path by reusing the scan registers, while ensuring high resource utilization. The experimental results demonstrate the effectiveness of the new technique to synthesize easily testable data paths, with nominal hardware overhead, while maintaining the performance of the designs. The partial scan overhead incurred by the technique is significantly less than that of a gate-level partial scan approach. >

Optimisation efficiency in behavioural synthesis

Behavioural synthesis is the process whereby the mapping of system operation (behaviour) onto a physical circuit is essentially automated. In general, there are many ways in which a given design can be realised and each alternative design will have different physical parameters (area, speed and power dissipation being the most common). One of the key features of a good silicon compiler is that it allows the user to explore the 'design space' corresponding to the behavioural description; this means that the system must be capable of producing alternative (but behaviourally equivalent) designs relatively quickly. This paper describes the optimisation technique used in the MOODS (multiple objective optimisation behavioural synthesis) system and looks at the efficiency of the various subprocesses. The conclusions are that even for a large synthesis task, the time taken taken for MOODS to generate alternative designs is sufficiently low that the user response (in evaluating alternative designs) is essentially the rate limiting step in the overall design process. Typically, MOODS can generate 35 designs/second for a behavioural description containing 41 primitive operations running on a Sun SPARCstation LX.

Multiple objective optimisation in a behavioural synthesis system

The paper describes the implementation of an ‘intelligent’ silicon compiler that provides the ability to optimise a design, given as a behavioural description, with respect to multiple objectives. The user submits goals or objectives to the system, named MOODS, which automatically finds an optimal solution in the context of the user-specified constraints. The MOODS system provides a sound basis for multiple objective optimisation and allows the user to characterise and explore the design space. An accurate representation of the implementations in the design space is ensured by feeding up technology-dependent information from a cell library. This data is used in a global cost function which guides the application of transformations on a multilevel representation of the design. The results obtained show that designs can be produced which meet users’ objectives and that a varied set of implementations can be synthesised from a single behavioural specification. The resulting characteristics of the set of implementations enable the design space to be characterised.