Behavioral Fault Simulation Research Articles

BFS-DEVS: A general DEVS-based formalism for behavioral fault simulation

Discrete event modeling allows designing an easy-to-handle and reusable representation of a system but, in its classical form, only permits one simulation at a time for a system. Concurrent and Comparative Simulation (CCS) with Multi-List Propagation (MLP) appears to be an adapted solution, by providing a way to perform several simulations in a single execution run. Concurrent Fault Simulation (CFS) has been one of the first applications of the CCS. The main obstacles to a wide use of this technique are the high complexity of the concurrent simulation algorithms, along with the difficulty to integrate them in a simulation kernel. We focus in this paper on the CFS with MLP of systems described in the new BFS-DEVS formalism, which is an evolution of the original DEVS simulator that integrates the CCS algorithm. The application is performed in the behavioral digital domain of systems described in the VHDL language.

Behavioral test generation/fault simulation

A complete behavioral fault simulation and automatic test pattern generation (ATPG) system for circuits modeled in VHDL has been presented in this research. Ten different behavioral fault models were selected and used to generate test patterns through fault simulation. One major advantage of the current system is that full VHDL (IEEE-STD 1076) constructs can be handled because fault simulation are performed by comparing the simulation results of good and faulty models utilizing a VHDL simulator. Areas of future research include the refinement of existing fault models, defining new behavioral fault models to reduce the gap between the behavioral fault models and gate-level failures, and the development of a better test pattern generator for target faults. Another valuable enhancement would be to run fault simulation in parallel, by embedding multiple faulty models into one test bench to simulate many faults concurrently. This would speed up the behavioral fault simulation in an efficient way. Gate-level fault simulation is not an effective solution for complex microcircuits. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC).

VHDL behavioral ATPG and fault simulation of digital systems

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation is becoming more complex, difficult, and costly. Furthermore, circuit designs are increasingly being developed through the use of powerful VLSI computer-aided design (CAD) synthesis tools which emphasize circuit descriptions using high-level representations of functional behavior, rather than physical architectures and layout. Behavior fault simulation applied to the top functional level models described using a hardware description language offers a very attractive alternative to these problems. A new way to simulate the behavioral fault models using the hardware description language (HDL), such as VHDL, is presented. Tests were generated by carrying out the behavioral fault simulation for a few circuit models. For comparison, a gate-level fault simulation on the equivalent circuit, produced via a synthesis tool, was used. The performance analysis shows that a very small number of test patterns generated by the behavioral automatic test pattern generation (ATPG)/fault simulation system detected around 98 percent of the testable gate-level faults that were detected by random test.