Beamformer Chips Research Articles

A 64-Element 28-GHz Phased-Array Transceiver With 52-dBm EIRP and 8–12-Gb/s 5G Link at 300 Meters Without Any Calibration

This paper presents a 64-element 28-GHz phased-array transceiver for 5G communications based on $2\times 2$ transmit/ receive (TRX) beamformer chips. Sixteen of the $2\times 2$ TRX chips are assembled on a 12-layer printed circuit board (PCB) together with a Wilkinson combiner/divider network and 28–32-GHz stacked-patch antennas. The 64-element array results in 1.1 dB and 8.9° rms amplitude and phase error, respectively, with no calibration due to the symmetric design of the $2\times 2$ beamformer chips and the PCB Wilkinson network. The effect of phase and amplitude mismatch between the 64 elements is analyzed and shown to have little impact on the 64-element array performance due to the averaging effects of phased arrays. Detailed pattern, effective isotropic radiated power (EIRP), and link measurements performed without any array calibration are presented and show the robustness of the symmetrical design technique. The phased array can scan to ±50° in azimuth ( $H$ -plane) and ±25° in elevation ( $E$ -plane) with low sidelobes and achieves a saturated EIRP of 52 dBm with 4-GHz 3-dB bandwidth. A 300-m wireless link is demonstrated with a record-setting data rate of 8–12 Gb/s over all scan angles using two 64-element TRX arrays and 16-/64-QAM waveforms.

A fully integrated 4-channel beamformer based on TTD phased array in 0.18μm CMOS

A fully integrated 4-channel beamformer based on TTD phased array is proposed in this paper. This architecture is especially suitable for MIMO systems which can increase throughput by improving multiplexing gain. A path-sharing true time delay (TTD) unit by using analog CMOS filter circuits is presented to realize flat time delay over 0.35–1 GHz. Compared to traditional MIMO architectures, highly multiplexed TTD reduces chip area and power consumption. The proposed beamformer can provide maximum scan angle of up to ±45°for four antennas with 10.5 cm spacing. The measurement results show that maximum delay is almost consistent with simulated results. Input signals from the same direction which reach different antennas, are delayed a different fixed time difference through different TTD units and have same phase at the output, realizing signal enhancement. The whole beamformer chip consumes 130 mA from a 1.8 V DC power supply, and has a total chip area of 4.65 mm × 4.30 mm.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a <inline-formula> <tex-math notation="LaTeX">$2\times 2$ </tex-math> </inline-formula> Beamformer Flip-Chip Unit Cell

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.

A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The RX beamformer chip includes 64 analog front-end branches including 64 non-uniform sampling ADCs, a FIFO/Adder, and an on-chip look-up table (LUT). The LUT stores the information on the rising edge timing of the non-uniform ADC sampling clocks. To include the LUT inside the beamformer chip, the LUT size was reduced by around 240 times by approximating an ADC-sample-time profile w.r.t. focal points (FP) along a scanline (SL) for a channel into a piece-wise linear form. The maximum error between the approximated and accurate sample times of ADC is eight times the sample time resolution (Ts) that is 1/32 of the ultrasound signal period in this work. The non-uniform sampling reduces the FIFO size required for digital beamforming by around 20 times. By applying a 9-dot image from Field-II program and 2-D ultrasound phantom images to the fabricated RX beamformer chip, the original images were successfully reconstructed from the measured output. The chip in a 0.13-um CMOS occupies 30.25 [Formula: see text] and consumes 605 mW.

An analog-digital hybrid RX beamformer chip with non-uniform sampling for ultrasound medical imaging with 2D CMUT array.

To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for the ultrasound medical imaging with a 2D CMUT array. The chip retrieved successfully two B-mode phantom images with a steering angle from -45 (°) to +45 (°), the maximum delay range of 8 μs, and the delay resolution of 6.25 ns. An analog-digital hybrid BF (HBF) is chosen for the proposed chip to utilize the easy beamforming operation in the digital domain and also to reduce chip area by minimizing the number of ADCs. The chip consists of eight analog beamformers (ABF) for the 1st-stage and a digital beamformer (DBF) for the 2nd-stage. The two-stage architecture reduces the memory area of both ABF and DBF by around four times. The DBF circuit is divided into three steps to further reduce the digital FIFO memory area by around twice. Coupled with the non-uniform sampling scheme, the proposed two-stage HBF chip reduces the total memory area by around 40 times compared to the uniform-sampling single-stage BF chip. The chip fabricated in a 0.13- μm CMOS process occupies the area of 19.4 mm(2), and dissipates 1.14 W with the analog supply of 3.3 V and the digital supply of 1.2 V.

Integrated Photonic ${\rm K}_{\rm u}$-Band Beamformer Chip With Continuous Amplitude and Delay Control

We present the first demonstration of a broadband and continuously tunable integrated optical beamforming network (IOBFN) capable of providing continuously tunable true-time-delay up to 236 ps over the entire DVB-S band (10.7-12.75 GHz), realized with a CMOS compatible process. The tunable delays are based on reconfigurable optical ring resonators in conjunction with a single optical sideband filter integrated on the same optical chip. The delays and filter responses are software programmable. Four tunable delay lines are integrated on a single chip and configured to feed a 16-element linear antenna array. The broadband beam steering capability of the proposed IOBFN is demonstrated by the squint-free antenna pattern generated from the measured RF amplitude and phase responses of the optical delay line.

A Two-Channel 8–20-GHz SiGe BiCMOS Receiver With Selectable IFs for Multibeam Phased-Array Digital Beamforming Applications

An 8-20-GHz two-channel SiGe BiCMOS receiver is presented for digital beam-forming applications. The receiver is based on a dual-down-conversion architecture with selectable IF for interference mitigation and results in a channel gain (in-phase and quadrature paths) of 46-47 dB at 11-15 GHz and >;36 dB at 8-20 GHz with an instantaneous bandwidth of 150 MHz. A 2-bit gain control (0-16 dB) is also provided at baseband. The mea sured noise figure (NF) is <;4.1 dB (3.1 dB at 15-16 GHz) and is independent of the gain state. The measured OPldB is -10 dBm and the input PldB is -56 to -40 dBm at 15 GHz depending on the gain, which is sufficient for satellite applications. The on-chip channel-to-channel coupling is <; -48 dB. The measured evanescent mode is <;3% for a 1-Ms/s quadrature phase-shift keying (QPSK) modulation at 8-20 GHz, and <;1.8% for a 0.1-, 1-, and 10-Ms/s QPSK, 16 quadrature amplitude modulation (QAM), and 64-QAM modulations at 15 GHz. The chip is fabricated using a 0.18-μm SiGe BiCMOS process, has electrostatic discharge protection on the RF and dc pads, consumes 70 mA per channel from a 3.0-V power supply, and is 2.6 × 2.2 mm2, including all pads. A 15-GHz eight-element phased array with an NF <;3.8 dB is also demonstrated with multiple simultaneous beam performance. To our knowledge, this is the first two-channel 8-20-GHz beam-forming chip in SiGe BiCMOS technology.

A $V$-Band Switched Beam-Forming Antenna Module Using Absorptive Switch Integrated With 4$\,\times\,$4 Butler Matrix in 0.13-$\mu{\hbox {m}}$ CMOS

A beam-forming antenna module is demonstrated using an integrated CMOS beam-former chip and a simple two-metal layer printed circuit board at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V$</tex></formula> -band. The beam-former circuit integrates an absorptive single-pole four-throw switch together with a 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 4 Butler matrix using a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process. The entire insertion loss of the integrated beam former integrated circuit (IC) is around 7.5 dB at 60 GHz, among which 3 dB is attributed to the Butler matrix. The overall phase error is within <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\pm}$</tex></formula> 12%. The antenna module employs backside radiation structure using series-fed patch antenna arrays to suppress parasitic radiation. The measured radiation pattern shows good agreement with the simulation. To the best of our knowledge, this is the first demonstration of the beam-forming antenna module using a single-chip CMOS switched beam-former IC at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V$</tex> </formula> -band

R&amp;D at Nançay for radio astronomy detectors and systems

Nançay radio astronomy station teams are involved in several aspects of the Research and Development (R&D) for radio astronomy detectors and systems: i) Microelectronics: Low Noise Amplifiers (LNA), receiver on chip and system in package. The long-term goal is to provide sub-systems for the future Square Kilometer Array and its Pathfinders. A beamformer chip has been integrated in the FP6 SKADS dense aperture array technology demonstrator EMBRACE. Wide band SiGe LNAs are developed, beamformers with in-chip control are studied and more complex integrated receivers are designed for the european Aperture Array Verification Programme demonstrator. ii) Digital signal processing: EMBRACE beamforming has been implemented in the digital backend and RFI-mitigation oriented signal processing has been designed for realtime systems, including work for FP6 SKADS and FP7 PrepSKA. iii) A study of Phased Array Feeds has started in 2008, in order to study the radio electric properties of PAFs at the focus of large F/D telescopes, such as the Nançay Radio Telescope, as well as to test PAF systems in collaboration with the SPP/IRFU and LAL/IN2P3 laboratories.

Time domain beamforming ASIC for a handheld bistatic imaging sonar system

A high-resolution, handheld imaging sonar system has been developed by Teratech Corporation for the U.S. Navy. This is a 192-channel, dual-frequency bistatic sonar for Navy divers performing search and survey missions for underwater explosives. The goal is to provide the most compact and energy-efficient imaging system for the divers. The low power and small volume are a result of the development of Teratech’s Charge Domain Processing (CDP) technology. This technology has led to the development of a low-power 64-channel beamformer chip. As a result, only three beamformer chips are needed for the 192-element array. Until now, implementation of small, low-power sonar systems containing this many elements and forming enough beams to create an image was considered impossible. Test results and acoustic images obtained in Teratech’s acoustic test tank will be presented. [Work sponsored by ONR and OSD Small Business Innovative Research Program, Program Manager, Mr. Bruce Johnson, Naval Explosive Ordnance Disposal Technology Division.]

Development of a handheld bistatic imaging sonar system for underwater search and survey

A high resolution, handheld imaging sonar system is under development by Teratech Corporation for the U.S. Navy. This is a 192 channel, dual frequency bistatic sonar for Navy divers performing search and survey missions for underwater explosives. Our goal is to provide the most compact and energy efficient imaging system for the divers. The system consists of a self-contained handheld unit and a head mounted display integrated into the divers mask. The low power and small volume are a result of the development of Teratechs Charge Domain Processing (CDP) technology. This technology has led to the development of a low power 64-channel beamformer chip. As a result, only three beamformer chips will be required for the 192 channels. Until now, the implementation of small, low power sonar systems containing this many elements and forming enough beams to create an image was considered impossible. Progress in the development of this product will be presented. In-water testing is planned for late summer 2003. Experimental results and test images available will be presented at the conference. [Work sponsored by ONR and OSD Small Business Innovative Research Program, Program manager, Mr. Bruce Johnson, Naval Explosive Ordnance Disposal Technology Division.]