Integrated injection logic (I2L) gates have been fabricated using electron-beam lithography, ion implanatation, and advanced I2L design technology. Minimum line widths of 1.25 μm were used to delineate structures five times smaller in area than obtained with conventional design rules. Improved geometry control was achieved by using shallow diffusions and thin epi (∠1.2 μm). PBS positive resist was used to pattern and etch oxides and TI309 negative resist was used to mask etching of Al/Si and Al/Cu metallizations. Thick PMMA was used as an implant mask for 300-keV p− intrinsic base implant. Chip-by-chip alignment of 2.5×2.5 mm2 fields yielded level to level registration accuracy of 0.2–0.4 μm. Using a 25-stage ring oscillator as a test vehicle, gate delays of ∠6 ns at 100 μA/gate have been measured on 5-collector, n+ guard ring device structures. These devices also yielded a speed–power product five times lower than that of similar conventionally sized devices.