BDD-based Approach Research Articles

A BDD-Based Approach to Finite-Time Control of Boolean Networks

A BDD-Based Approach to Finite-Time Control of Boolean Networks

A BDD-Based Approach to Model Reduction of Boolean Networks

A BDD-Based Approach to Model Reduction of Boolean Networks

Leveraging decision diagrams to solve two-stage stochastic programs with binary recourse and logical linking constraints

We generalize an existing binary decision diagram-based (BDD-based) approach of Lozano and Smith (MP, 2022) to solve a special class of two-stage stochastic programs (2SPs) with binary recourse, where the first-stage decisions impact the second-stage constraints. First, we extend the second-stage problem to a more general setting where logical expressions of the first-stage solutions enforce constraints in the second stage. Then, as our primary contribution, we introduce a complementary problem, that appears more naturally for many of the same applications of the former approach, and a distinct BDD-based solution method, that is more efficient than the existing BDD-based approach on commonly applicable problem classes. In the novel problem, second-stage costs, rather than constraints, are impacted by expressions of the first-stage decisions. In both settings, we convexify the second-stage problems using BDDs and parameterize either the BDD arc costs or capacities with first-stage solutions. We extend this work by incorporating conditional value-at-risk and propose the first decomposition method for 2SP with binary recourse and a risk measure. We apply these methods to a novel stochastic problem, namely stochastic minimum dominating set problem, and present numerical results to support their effectiveness.

AllSynth: A BDD-based approach for network update synthesis

AllSynth: A BDD-based approach for network update synthesis

Precise Quantitative Analysis of Binarized Neural Networks: A BDD-based Approach

As a new programming paradigm, neural-network-based machine learning has expanded its application to many real-world problems. Due to the black-box nature of neural networks, verifying and explaining their behavior are becoming increasingly important, especially when they are deployed in safety-critical applications. Existing verification work mostly focuses on qualitative verification, which asks whether there exists an input (in a specified region) for a neural network such that a property (e.g., local robustness) is violated. However, in many practical applications, such an (adversarial) input almost surely exists, which makes a qualitative answer less meaningful. In this work, we study a more interesting yet more challenging problem, i.e.,quantitativeverification of neural networks, which asks how often a property is satisfied or violated. We target binarized neural networks (BNNs), the 1-bit quantization of general neural networks. BNNs have attracted increasing attention in deep learning recently, as they can drastically reduce memory storage and execution time with bit-wise operations, which is crucial in recourse-constrained scenarios, e.g., embedded devices for Internet of Things. Toward quantitative verification of BNNs, we propose a novel algorithmic approach for encoding BNNs as Binary Decision Diagrams (BDDs), a widely studied model in formal verification and knowledge representation. By exploiting the internal structure of the BNNs, our encoding translates the input-output relation of blocks in BNNs to cardinality constraints, which are then encoded by BDDs. Based on the new BDD encoding, we develop a quantitative verification framework for BNNs where precise and comprehensive analysis of BNNs can be performed. To improve the scalability of BDD encoding, we also investigate parallelization strategies at various levels. We demonstrate applications of our framework by providing quantitative robustness verification and interpretability for BNNs. An extensive experimental evaluation confirms the effectiveness and efficiency of our approach.

Reliability Analysis of IoT Networks with Community Structures

Network infrastructure and connectivity in the Internet of Things (IoT) applications are becoming increasingly complex and heterogeneous, opening up many challenges including reliability. Many real-world networks exhibit community structure, where the networked devices can be easily grouped into sets with dense internal connections but sparse connections between different sets. Examples of such community-structured networks can be found in diverse IoT applications such as smart grids, smart cities, and military systems. Due to these critical applications, reliability analysis is of great significance for robust and safe design and operation of IoT networks. In this paper, we present an efficient binary decision diagram (BDD)-based approach to analyze the reliability of an IoT network with community structure and subject to random link failures. As efficiency of the BDD-based approach heavily depends on the ordering of input variables, we make novel contributions by proposing efficient ordering heuristics for individual communities and the whole IoT network composed of multiple communities. Performance of the proposed ordering heuristics for IoT networks with either linear interconnection pattern or random interconnection pattern is investigated. As demonstrated through comprehensive experiments, the proposed ordering heuristics provide significantly better performance in model complexity than the traditional ordering heuristics.

A BDD-Based Approach for Designing Maximally Permissive Deadlock Avoidance Policies for Complex Resource Allocation Systems

In order to develop a computationally efficient implementation of the maximally permissive deadlock avoidance policy (DAP) for complex resource allocation systems (RAS), a recent approach focuses on the identification of a set of critical states of the underlying RAS state-space, referred to as minimal boundary unsafe states. The availability of this information enables an expedient one-step-lookahead scheme that prevents the RAS from reaching outside its safe region. The work presented in this paper seeks to develop a symbolic approach, based on binary decision diagrams (BDDs), for efficiently retrieving the (minimal) boundary unsafe states from the underlying RAS state-space. The presented results clearly demonstrate that symbolic computation enables the deployment of the maximally permissive DAP for complex RAS with very large structure and state-spaces with limited time and memory requirements. Furthermore, the involved computational costs are substantially reduced through the pertinent exploitation of the special structure that exists in the considered problem.

Symbolic counterexample generation for large discrete-time Markov chains

This paper presents several symbolic counterexample generation algorithms for discrete-time Markov chains (DTMCs) violating a PCTL formula. A counterexample is (a symbolic representation of) a sub-DTMC that is incrementally generated. The crux to this incremental approach is the symbolic generation of paths that belong to the counterexample. We consider two approaches. First, we extend bounded model checking and develop a simple heuristic to generate highly probable paths first. We then complement the SAT-based approach by a fully (multi-terminal) BDD-based technique. All symbolic approaches are implemented, and our experimental results show a substantially better scalability than existing explicit techniques. In particular, our BDD-based approach using a method called fragment search allows for counterexample generation for DTMCs with billions of states (up to 1015).

Efficient synthesis of feature models

ContextVariability modeling, and in particular feature modeling, is a central element of model-driven software product line architectures. Such architectures often emerge from legacy code, but, creating feature models from large, legacy systems is a long and arduous task. We describe three synthesis scenarios that can benefit from the algorithms in this paper. ObjectiveThis paper addresses the problem of automatic synthesis of feature models from propositional constraints. We show that the decision version of the problem is NP-hard. We designed two efficient algorithms for synthesis of feature models from CNF and DNF formulas respectively. MethodWe performed an experimental evaluation of the algorithms against a binary decision diagram (BDD)-based approach and a formal concept analysis (FCA)-based approach using models derived from realistic models. ResultsOur evaluation shows a 10 to 1,000-fold performance improvement for our algorithms over the BDD-based approach. The performance of the DNF-based algorithm was similar to the FCA-based approach, with advantages for both techniques. We identified input properties that affect the runtimes of the CNF- and DNF-based algorithms. ConclusionsOur algorithms are the first known techniques that are efficient enough to be used on dependencies extracted from real systems, opening new possibilities of creating reverse engineering and model management tools for variability models.

Bounded Model Checking of ETL Cooperating with Finite and Looping Automata Connectives

As a complementary technique of the BDD-based approach, bounded model checking (BMC) has been successfully applied to LTL symbolic model checking. However, the expressiveness of LTL is rather limited, and some important properties cannot be captured by such logic. In this paper, we present a semantic BMC encoding approach to deal with the mixture ofETLfandETLl. Since such kind of temporal logic involves both finite and looping automata as connectives, all regular properties can be succinctly specified with it. The presented algorithm is integrated into the model checker ENuSMV, and the approach is evaluated via conducting a series of imperial experiments.

A BDD-Based Approach for Modeling Plant and Supervisor by Extended Finite Automata

In this paper, we settle some problems that are encountered when modeling and synthesizing complex industrial systems by the supervisory control theory. First, modeling such huge systems with explicit state-transition models typically results in an intractable model. An alternative modeling approach is to use extended finite automata (EFAs), which is an augmentation of ordinary automata with variables. The main advantage of utilizing EFAs for modeling is that more compact models are obtained. The second problem concerns the ease to understand and implement the supervisor. To handle this problem, we represent the supervisor in a modular manner by extending the original EFAs by compact conditional expressions. This will provide a framework for the users where they can both model their system and obtain the supervisor in form of EFAs. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams (BDDs). All computations that are performed in this framework are based on BDD operations. The framework has been implemented in a supervisory control tool and applied to industrially relevant benchmark problems.

Parallel BDD-based monolithic approach for acoustic fluid-structure interaction

Parallel BDD-based monolithic algorithms for acoustic fluid-structure interaction problems are developed. In a previous study, two schemes, NN-I + CGC-FULL and NN-I + CGC-DIAG, have been proven to be efficient among several BDD-type schemes for one processor. Thus, the parallelization of these schemes is discussed in the present study. These BDD-type schemes consist of the operations of the Schur complement matrix-vector (Sv) product, Neumann-Neumann (NN) preconditioning, and the coarse problem. In the present study, the Sv product and NN preconditioning are parallelized for both schemes, and the parallel implementation of the solid and fluid parts of the coarse problem is considered for NN-I + CGC-DIAG. The results of numerical experiments indicate that both schemes exhibit performances that are almost as good as those of single solid and fluid analyses in the Sv product and NN preconditioning. Moreover, NN-I + CGC-DIAG appears to become more efficient as the problem size becomes large due to the parallel calculation of the coarse problem.

Cycle elimination for invocation graph-based context-sensitive pointer analysis

Context Pointer analysis is an important building block of optimizing compilers and program analyzers for C language. Various methods with precision and performance trade-offs have been proposed. Among them, cycle elimination has been successfully used to improve the scalability of context-insensitive pointer analyses without losing any precision. Objective In this article, we present a new method on context-sensitive pointer analysis with an effective application of cycle elimination. Method To obtain similar benefits of cycle elimination for context-sensitive analysis, we propose a novel constraint-based formulation that uses sets of contexts as annotations. Our method is not based on binary decision diagram (BDD). Instead, we directly use invocation graphs to represent context sets and apply a hash-consing technique to deal with the exponential blow-up of contexts. Result Experimental results on C programs ranging from 20,000 to 290,000 lines show that applying cycle elimination to our new formulation results in 4.5 ×speedup over the previous BDD-based approach. Conclusion We showed that cycle elimination is an effective method for improving the scalability of context-sensitive pointer analysis.

BDD-Based Approach to the Verification of Feature Models

PDF HTML阅读 XML下载 导出引用 引用提醒 基于二分决策图的特征模型验证方法 DOI: 作者: 作者单位: 作者简介: 通讯作者: 中图分类号: 基金项目: Supported by the National Natural Science Foundation of China under Grant Nos.60528006, 60703065, 60873059 (国家自然科学基金); the National High-Tech Research and Development Plan of China under Grant Nos.2006AA01Z156, 2007AA01Z123 (国家高技术研究发展计划(863)); the National Basic Research Program of China under Grant No.2005CB321805 (国家重点基础研究发展计划(973)) BDD-Based Approach to the Verification of Feature Models Author: Affiliation: Fund Project: 摘要 | 图/表 | 访问统计 | 参考文献 | 相似文献 | 引证文献 | 资源附件 | 文章评论 摘要:特征模型是领域分析活动产生的具有复用价值的软件需求模型.对特征模型的复用通常采用定制的方式.特征模型定制中的一个重要问题是验证问题.该问题的存在是因为特征之间往往具有一定的约束关系,而一个合法的定制结果必须保证特征之间所有约束关系的被满足性.由于特征模型验证问题NP-hard所具有的性质,如何高效地进行特征模型的验证就成为一件相对困难的事情.在深入挖掘特征模型验证问题特殊性的基础上,将这种特殊性和二分决策图的结构特点进行了有效的结合,提出了一种通过对二分决策图的一次遍历即能实现特征模型验证的方法.需要指出的是,该方法并非试图在一般意义上解决特征模型验证问题中NP-hard的困难性,而是尽可能地利用该问题的特殊性,以提高处理特征模型定制问题的规模和效率.实验数据表明,相比较以前采用的验证方法,基于BDD(binary decision diagram)的方法在处理特征模型验证问题的规模和效率上都具有显著的提高. Abstract:The feature model is a reusable requirements model generated from the domain analysis. The reuse of feature models is usually achieved by a customizing-based approach. One important issue in feature models’ customization is the verification problem, caused by the fact that there are usually constraints among features, and that a valid customizing result must satisfy all these constraints. Because of the NP-hard nature of this problem, it is usually difficult to verify feature models in an efficient way. This paper presents a BDD (binary decision diagram)-based approach to verifying feature models by only traversing once to the nodes in BDDs, an approach that makes an efficient use of the BDD data structures based on the unique characteristics of feature models’ verification. It should be pointed out that this approach does not attempt to resolve the NP-hard difficulty of the verification problem in a general sense, but just tries to improve the scalability and efficiency of methods for feature models’ verification based on the utilization of this problem’s uniqueness. Experimental results show that this BDD-based approach is more efficient and can verify more complex feature models than the previous method. 参考文献 相似文献 引证文献

A reliability analysis method using binary decision diagrams in phased mission planning

The use of autonomous systems is becoming increasingly common in many fields. A significant example of this is the ambition to deploy unmanned aerial vehicles (UAVs) for both civil and military applications. In order for autonomous systems such as these to operate effectively, they must be capable of making decisions regarding the appropriate future course of their mission responding to changes in circumstance in as short a time as possible. The systems will typically perform phased missions and, owing to the uncertain nature of the environments in which the systems operate, the mission objectives may be subject to change at short notice. The ability to evaluate the different possible mission configurations is crucial in making the right decision about the mission tasks that should be performed in order to give the highest possible probability of mission success. Because binary decision diagrams (BDDs) may be quickly and accurately quantified to give measures of the system reliability it is anticipated that they are the most appropriate analysis tools to form the basis of a reliability-based prognostics methodology. The current paper presents a new BDD-based approach for phased mission analysis, which seeks to take advantage of the proven fast analysis characteristics of the BDD and enhance it in ways that are suited to the demands of a decision-making capability for autonomous systems. The BDD approach presented allows BDDs representing the failure causes in the different phases of a mission to be constructed quickly by treating component failures in different phases of the mission as separate variables. This allows flexibility when building mission phase failure BDDs because a global variable ordering scheme is not required. An alternative representation of component states in time intervals allows the dependencies to be efficiently dealt with during the quantification process. Nodes in the BDD can represent components with any number of failure modes or factors external to the system that could affect its behaviour, such as the weather. Path simplification rules and quantification rules are developed that allow the calculation of phase failure probabilities for this new BDD approach. The proposed method provides a phased mission analysis technique that allows the rapid construction of reliability models for phased missions and, with the use of BDDs, rapid quantification.

Verification of a network ASIC Component using Bounded Model Checking

Recently, a new technique called bounded model checking has been proposed that uses fast satisfiability solvers instead of binary decision diagrams (BDDs). This paper presents the experiences on formally verifying the behaviour and implementation of an Asynchronous Transfer Mode (ATM) network switching module using Nusmv2 tool. A number of properties described by linear temporal logic (LTL) are provided, and their verification in reasonable central processing unit (CPU) time is accomplished by estimating a more precise bound k which is determined by the circuit structure. Moreover, equivalence checking between the structural and behavioural descriptions of the whole switch module as one model is performed, and the results compared with those of the BDD-based approach. Based on that experience, bounded model checking will be the mainstream of industrial chip verification.

Language-Emptiness Checking of Alternating Tree Automata Using Symbolic Reachability Analysis

Alternating tree automata and AND/OR graphs provide elegant formalisms that enable branching- time logics to be verified in linear time. The seminal work of Kupferman et al. [Orna Kupferman, Moshe Y. Vardi, and Pierre Wolper. An automata-theoretic approach to branching-time model checking. J. ACM, 47(2):312–360, 2000] showed that 1) branching-time model checking is reducible to the language non-emptiness checking of the product of two alternating automata representing the model and property under verification, and 2) the non-emptiness problem can be solved by performing a search on an AND/OR graph representing this product. Their algorithm, however, can only be implemented in an explicit-state model checker because it needs stacks to detect accept and reject runs. In this paper, we propose a BDD-based approach to check the language non-emptiness of the product automaton. We use a technique called “state recording” from Schuppan and Biere [Viktor Schuppan and Armin Biere. Efficient reduction of finite state model checking to reachability analysis. Int. Journal on Software Tools for Technology Transfer (STTT), 5(2–3):185–204, 2004] to emulate the stack mechanism from explicit-state model checking. This technique allows us to transform the product automaton into a well-defined AND/OR graph. We develop a BDD-based reachability algorithm to efficiently determine whether a solution graph for the AND/OR graph exists and thereby solve the model-checking problem. While “state recording” increases the size of the state space, the advantage of our approach lies in the memory saving BDDs can offer and the potential it opens up for optimisation of the reachability analysis. We remark that this technique always detects the shortest counter-example.

BDD-based decision procedures for the modal logic K ★

We describe BDD-based decision procedures for the modal logic K . Our approach is inspired by the automata-theoretic approach, but we avoid explicit automata construction. Instead, we compute certain fixpoints of a set of types — which can be viewed as an on-the-fly emptiness of the automaton. We use BDDs to represent and manipulate such type sets, and investigate different kinds of representations as well as a “level-based” representation scheme. The latter turns out to speed up construction and reduce memory consumption considerably. We also study the effect of formula simplification on our decision procedures. To prove the viability of our approach, we compare our approach with a representative selection of other approaches, including a translation of K to QBF. Our results indicate that the BDD-based approach dominates for modally heavy formulae, while search-based approaches dominate for propositionally heavy formulae.

BDD-BASED ANALYSIS OF GAPPED q-GRAM FILTERS

Recently, there has been a surge of interest in gapped q-gram filters for approximate string matching. Important design parameters for filters are for example the value of q, the filter-threshold and in particular the shape (aka seed) of the filter. A good choice of parameters can improve the performance of a q-gram filter by orders of magnitude and optimizing these parameters is a nontrivial combinatorial problem. We describe a new method for analyzing gapped q-gram filters. This method is simple and generic. It applies to a variety of filters, overcomes many restrictions that are present in existing algorithms and can easily be extended to new filter variants. To implement our approach, we use an extended version of BDDs (Binary Decision Diagrams), a data structure that efficiently represents sets of bit-strings. In a second step, we define a new class of multi-shape filters and analyze these filters with the BDD-based approach. Experiments show that multi-shape filters can outperform the best single-shape filters, which are currently in use, in many aspects. The BDD-based algorithm is crucial for the design and analysis of these new and better multi-shape filters. Our results apply to the k-mismatches problem, i.e. approximate string matching with Hamming distance.

A BMC-based formulation for the scheduling problem of hardware systems

Hardware scheduling is a well-known and well-studied problem. This paper defines a new SAT-based formulation of automata-based scheduling and proposes for the first time a completely new resolution algorithm based on SAT solvers and bounded model checking (BMC). The new formulation is specifically suited to control-dominated applications. Alternative executions are modeled as concurrency, where alternative behaviors are followed in parallel. This approach produces "single-path" scheduling traces instead of standard "treelike" solutions, thus enabling the use of BMC. This choice, however, creates the problem that resource bounds are treated incorrectly, due to the artificial concurrency modeling alternative behaviors. We then discuss how to take this into account, either by modifying the SAT solver or by adding extra clauses. Thus we are able to exploit SAT-based BMC to find the desired minimum latency schedule. Our method shows significant improvements in terms of both computational efficiency and modeling power, when compared to the BDD-based approach, and in terms of the optimality of the results when compared to heuristic methods.