BCH Decoder Research Articles

The hybrid method for finding the roots of a polynomial over finite fields based on affine expansion

This paper proposes a hybrid method to find the roots of a polynomial in a finite field based on combining the polynomial decomposition into the sum of multiples of the affine polynomial with the analytical method to find the roots of low-order polynomials. The proposed method allows a significant reduction in complexity and is applicable in the design of low-latency BCH and Reed-Solomon decoders.

Deep Learning Algorithms for BCH Decoding in Satellite Communication

Deep learning is widely used in various fields due to the advancement of algorithms, the enrichment of high-efficiency databases, and the increase in computing power. Especially in the satellite communication, the learning and parallel computing capabilities of neural networks make them ideal for decoding. Many researchers have recently applied deep learning neural networks to decode high-density parity check (HDPC) codes (such as BCH and RS code), improving the decoder’s performance. This review aims to provide general insights on applying neural network decoders to satellite communications. Due to the neural network’s learning ability, the neural network-based decoder can be trained to change the weights, thereby reducing the influence of non-white noise in satellite communications, such as the influence between the satellite and the terrestrial network and the mutual interference within the satellites. To compensate for non-white noise, shortest circles in Tanner graph and unreliable information, a decoder system model for satellite communication constructed by three neural networks is presented.

Low latency BCH decoder using the affine polynomial over the finite field

The paper proposes a low latency BCH decoder with low complexity using parallel computation and simplifying locating errors by finding the roots of the affine polynomial over finite fields. The proposed design can be implemented on low-cost hardware platforms while applicable in very low latency information systems.

Don’t Reject This: Key-Recovery Timing Attacks Due to Rejection-Sampling in HQC and BIKE

Well before large-scale quantum computers will be available, traditional cryptosystems must be transitioned to post-quantum (PQ) secure schemes. The NIST PQC competition aims to standardize suitable cryptographic schemes. Candidates are evaluated not only on their formal security strengths, but are also judged based on the security with regard to resistance against side-channel attacks. Although round 3 candidates have already been intensively vetted with regard to such attacks, one important attack vector has hitherto been missed: PQ schemes often rely on rejection sampling techniques to obtain pseudorandomness from a specific distribution. In this paper, we reveal that rejection sampling routines that are seeded with secretdependent information and leak timing information result in practical key recovery attacks in the code-based key encapsulation mechanisms HQC and BIKE.Both HQC and BIKE have been selected as alternate candidates in the third round of the NIST competition, which puts them on track for getting standardized separately o the finalists. They have already been specifically hardened with constant-time decoders to avoid side-channel attacks. However, in this paper, we show novel timing vulnerabilities in both schemes: (1) Our secret key recovery attack on HQC requiresonly approx. 866,000 idealized decapsulation timing oracle queries in the 128-bit security setting. It is structurally different from previously identified attacks on the scheme: Previously, exploitable side-channel leakages have been identified in the BCH decoder of a previously submitted HQC version, in the ciphertext check as well as in the pseudorandom function of the Fujisaki-Okamoto transformation. In contrast, our attack uses the fact that the rejection sampling routine invoked during the deterministic re-encryption of the decapsulation leaks secret-dependent timing information, which can be efficiently exploited to recover the secret key when HQC is instantiated with the (now constant-time) BCH decoder, as well as with the RMRS decoder of the current submission. (2) From the timing information of the constant weight word sampler in the BIKE decapsulation, we demonstrate how to distinguish whether the decoding step is successful or not, and how this distinguisher is then used in the framework of the GJS attack to derive the distance spectrum of the secret key, using 5.8 x 107 idealized timing oracle queries. We provide details and analyses of the fully implemented attacks, as well as a discussion on possible countermeasures and their limits.

Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board.

Efficient Sub-Codeword Key Equation Solver for Generalized Integrated Interleaved BCH Decoder

Generalized integrated interleaved (GII) error-correcting codes nest sub-codewords to form codewords of more powerful codes. They can achieve hyper-speed decoding with good error correction capability. For GII codes built on BCH codes, the first decoding stage is to decode individual BCH sub-words. This stage largely determines the throughput and dominates the area of the overall decoder. Unlike that in traditional BCH decoding, longer polynomials need to be kept in the key-equation solver (KES) step of the first stage in order to continue the KES step in the second-stage nested decoding of GII codes. To take advantage of the very fast storage class memories (SCMs), GII codes with 3-error-correcting BCH sub-codewords can be utilized. This brief proposes a low-complexity and high-speed design for the KES of 3-error-correcting BCH sub-word decoding. Formulas are developed to compute the KES results directly instead of utilizing the traditional iterative process. More importantly, through analyzing the properties of the involved variables, the coefficients are scaled and reformulated to substantially reduce the complexity. Detailed hardware implementation architectures are also developed in this brief. Our design achieves three times throughput with 20.2% smaller area than the best prior design for a code over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$GF(2^{10})$ </tex-math></inline-formula> .

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and control lines without storage.

Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board.

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board.

Reduced complexity hard‐ and soft‐input BCH decoding with applications in concatenated codes

Error correction coding for optical communication and storage requires high rate codes that enable high data throughput and low residual errors. Recently, different concatenated coding schemes were proposed that are based on binary BCH codes with low error correcting capabilities. In this work, low-complexity hard- and soft-input decoding methods for such codes are investigated. We propose three concepts to reduce the complexity of the decoder. For the algebraic decoding we demonstrate that Peterson's algorithm can be more efficient than the Berlekamp–Massey algorithm for single, double, and triple error correcting BCH codes. We propose an inversion-less version of Peterson's algorithm and a corresponding decoding architecture. Furthermore, we propose a decoding approach that combines algebraic hard-input decoding with soft-input bit-flipping decoding. An acceptance criterion is utilised to determine the reliability of the estimated codewords. For many received codewords the stopping criterion indicates that the hard-decoding result is sufficiently reliable, and the costly soft-input decoding can be omitted. To reduce the memory size for the soft-values, we propose a bit-flipping decoder that stores only the positions and soft values of a small number of code symbols. This method significantly reduces the memory requirements and has little adverse effect on the decoding performance.

BCH CODES DECODER BASED ON EUCLID ALGORITHM

In the process of algebraic decoding of BCH codes over the field GF(q) with the word length n = qm-1, correcting t errors, both in the time and frequency domains, it is necessary to find the error locator polynomial ?(x) as the least polynomial for which the key equation. Berlekamp proposed a simple iterative scheme, which was called the Berlekamp-Messi algorithm, and is currently used in most practical applications. Comparative statistical tests of the proposed decoder and decoder using the Berlikamp-Messi algorithm showed that they differ slightly in decoding speed. The proposed algorithm is implemented in the environment in Turbo Pascal and can be used for the entire family of BCH codes by replacing the primitive Galois polynomial.

A Synthesizable BCH Decoder For DVB-S2 Satellite Communications

This paper presents the design of a BCH Decoder for digital satellite TV Communications. It includes an architecture design specification, as well as the results of FPGA prototyping and of the logical and physical synthesis in 65nm CMOS. Moreover, it can be used as a basis for BCH Decoder designs for other kind of communications or even storage error correction.

Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders

Generalized integrated interleaved (GII) codes nest linear block codewords to generate codewords belonging to stronger linear block codes. They can achieve very high throughput with excellent error-correcting capability. GII codes can be based on either Reed-Solomon (RS) or BCH codes. GII-BCH codes are the most promising candidate for error correction in next-generation terabit/s Flash and storage class memories, and optical communications. On the other hand, GII decoder implementation faces many challenges. In particular, the key equation solver (KES) in the nested decoding process causes not only clock frequency bottleneck but also large area. Although techniques have been developed recently to address these issues for GII-RS codes, they cannot be directly extended for binary GII-BCH codes if every other iteration of the nested KES is skipped to reduce the latency. Two instead of one higher-order syndromes need to be incorporated into each nested KES iteration and this makes the implementation much more challenging. In this paper, algorithmic reformulations and architectural modifications are developed to eliminate the clock frequency bottleneck and reduce the area of GII-BCH nested KES. Additionally, the number of processing elements is substantially reduced by analyzing the minimum number of coefficients to keep for the involved polynomials without undesirable degradation on the error-correcting performance. The critical path of the proposed scaled nested BCH KES architecture with reduced processing elements is only one multiplier and three adders. For an example GII-BCH code over ${GF}(2^{12})$ that has a ${t}_{v}=58$ -error-correcting code as the most powerful code generated by the nesting, our design also further reduces the area by 33%.

Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.

효율적인 SW 기반 BCH 부복호 구현에 관한 연구

본 논문에서는 무선통신인체망 표준으로 지정되어 있는 2비트 오류 정정 BCH 부호에 대한 효율적인 부복호기를 설계하고, 간단한 방법으로 오류 정정 효율을 개선할 수 있는 방법을 제안하였다. 2비트 오류정정이 가능한 BCH 부호는 비교적 간단한 오류정정 부호 방식으로, 부복호 과정의 효율화가 매우 중요하다. 본 논문에서 제안된 방식은 소프트웨어 기반으로 부복호 방식을 구현할 때, 그 효율성이 극대화 될 수 있는 방식이다. 나눗셈 나머지표를 이용한 부호화와 신드롬-오류위치 표를 이용한 복호 방식을 적용함으로써, 성능이 낮은 처리장치를 가진 시스템에서도 매우 적은 복잡도로 효율적인 부복호가 가능하다. 또한, 제안된 방법은 오류정정 복호 과정에서 수신된 비트의 신뢰도 정보가 낮은 비트를 선택적으로 비트 반전하는 방법을 적용하여, 연판정 복호와 유사한 장점을 취할 수 있도록 하였다. 본 논문에서 제시된 시뮬레이션 결과를 통하여, 제안된 방식이 비트오류율 성능 개선 효과가 있음을 보였으며, 그 효과는 모부호를 단축한 부호에서 더 크다는 것을 알 수 있다.

10.07uW Multi-Mode Baseband Transceiver for Encrypted Capsule Endoscopy

This paper proposes an ultra-low-power multi-mode baseband transceiver for capsule endoscopy. We set a new specification for capsule endoscopy to achieve ultra-low power and short-latency transceiver. The proposed baseband transceiver can operate multi-mode to transmit ten images per seconds depending on the presence of the lesion and the position of the capsule endoscope. The proposed one does not require memory and optimized all the logic and architecture levels. The proposed BCH decoder uses the early termination scheme to reduce the 51.16% of latency and 45.78% of power consumption, respectively. In addition, the advanced encryption standard (AES) processor protects the biomedical information. As a result, we implemented the proposed multi-mode baseband in Verilog-HDL and synthesized by using the Samsung 65 nm CMOS standard cell library. The proposed baseband shows 10.07 μW (0.9 V, @10 MHz) of total power consumption.

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

Simulation of coding layer of telecommand based on the Consultative Committee for Space Data Systems recommendation

Telecommand is a command sent to control a remote system or systems not directly connected to the place from which the telecommand is sent. In the telecommand process, there is a data processing process so that the command data that will be sent can be read / translated and processed accurately by the satellite. The Consultative Committee for Space Data Systems (CCSDS) provides recommendations for the telecommand process. CCSDS uses layering model to describe telecommand process, one of them is coding layer. This paper will talk about the simulation of coding layer of telecommand process based on CCSDS recommendation. The simulation involves randomization process, BCH encoding, and BCH decoding using MATLAB software. The result of this simulation shows encoding and decoding process successfully managed and produced data format which complies with CCSDS recommendation.

초고속 광통신을 위한 고성능 저면적 Iterative BCH 복호기 구조

초고속 광통신을 위한 고성능 저면적 Iterative BCH 복호기 구조

Primitive to non-primitive BCH codes: An instantaneous path shifting scheme for data transmission

In this paper, we present constructions of primitive and non-primitive BCH codes using monoid rings over the local ring [Formula: see text], with [Formula: see text]. We show that there exist two sequences [Formula: see text] and [Formula: see text] of non-primitive BCH codes (over [Formula: see text] and [Formula: see text], respectively) against primitive BCH codes [Formula: see text] of length [Formula: see text] and [Formula: see text] (over [Formula: see text] and [Formula: see text]), respectively. A technique is developed in an innovative way that enables the data path to shift instantaneously during transmission via the coding schemes of [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text]. The selection of the schemes is subject to the choice of better code rate or better error-correction capability of the code. Finally, we present a decoding procedure for BCH codes over Galois rings, which is also used for the decoding of BCH codes over Galois fields, based on the modified Berlekamp–Massey algorithm.

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture

An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this brief eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(210), the LUT size is reduced to 18% of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38% and the equivalent gate count by up to 40% compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.