Basic Switching Element Research Articles

Microwave Switch Architecture for Superconducting Integrated Circuits Using Magnetic Field-Tunable Josephson Junctions

We report on the design, fabrication, and measurement of a low-temperature microwave switch architecture that can be fully integrated on chip using single Josephson junctions and superconducting bias lines. The basic switching element used is a reflective single-pole-single-throw switch that is realized by tuning the critical current of a single Josephson junction by way of a local flux bias. A single-pole-single-throw switch is demonstrated at 4.2 K to have an on/off ratio in excess of 20 dB up to 12 GHz. This element is then incorporated into the design of a single-pole-double-throw switch that exhibits an on/off ratio above 20 dB up to 10 GHz. The switches require no intrinsic power dissipation in either state, and their performance was verified for input powers of -100 dBm to -60 dBm. S-parameter simulations using a simple lumped element model are in good agreement with the experimental data, allowing for the design to be extended to larger switch architectures.

Performance Evaluation of Datapath designs using FinFET and MOSFET

The VLSI Technology has been progressing significantly and the circuits which consume less power become major concern factor for designing todays ICs for Microprocessors and other various systems components. The Datapath is important part of a system. Adders, multipliers, and shift registers are the major components of data path unit of ALU. Almost all digital circuits and chips are made of MOSFET as the basic switching element. But same MOSFET suffers due to Short Channel Effects (SCEs) when scaled down to nano regime, which has promoted multigate device called FinFET. And this FinFET device overcomes the SCEs at technology nodes. In this paper 28T and 16T MOSFET and FinFET based full adders are designed. Using adders, 4x4 array multiplier is designed using both MOSFET and FinFET technology along with it Serial in Serial out shift register designs. The circuits designed based on MOSFET and FinFET are analyzed in terms of power and delay at various nodes. From the software characterization and analysis, it is understood that FinFET based circuits promise better performance at lower technology nodes like 22nm and 14nm than higher technology nodes in MOSFET like 250nm, 180nm, 90nm and 45nm. Hence FinFET becomes a promising device for future IC technology.

Compact design of photonic crystal ring resonator 2×2 routers as building blocks for photonic networks on chip

A highly compact 2×2 photonic crystal (PhC) passive wavelength router (λ-router) is proposed. The proposed λ-router exploits two photonic crystal ring resonators (PCRRs) having a 3.2 μm diameter and a broadband PhC waveguide crossing. The router topology, allowing assembly into higher-order matrices capable of connecting multiple transmitters with multiple receivers, can be exploited as a basic building block for the design, through a compositional approach, of more complex photonic integrated networks. The design criteria, derived by applying the finite difference time domain and the plane wave expansion methods, are reported. Moreover, the analysis of a 4×4λ-router configuration, obtained by assembling four 2×2 basic switching elements, is reported to highlight the potentiality of the basic routing element to be assembled into compact higher-order matrices that exhibit small footprints of 24 μm×24 μm and a maximum crosstalk between the ports equal to −20.1 dB.

Modeling WDM Wavelength Switching Systems for Use in GMPLS and Automated Path Computation

Network control planes have made an implicit assumption that the switching devices in a network are symmetric. In wavelength-switched optical networks even the most basic switching element, the reconfigurable add-drop multiplexer, is highly asymmetric. This paper presents a model of optical switching subsystems for use in generalized multiprotocol label switching (GMPLS), route selection, and wavelength assignment. The model covers a large class of switching subsystems without internal wavelength converters. The model is applied to a number of common optical technologies, and a compact encoding for use in the optical control plane is furnished along with a method for deriving a simplified graph representation.

3.5 GHz operation of a superconducting packet switch element

The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by a standard Nb trilayer process. Three-junction SQUIDs driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations.

Size–speed trade-off in optical switching elements

The basic building blocks of an interconnection network are the switching elements. We examine two optical implementations for a basic switching element: (1) ferroelectric liquid-crystal light valves and (2) Fabry-Perot étalons. For these two examples we report a trade-off between the size, i.e., the number of input and output channels, and the switching speed. We speculate that it may be a general property of optical switching elements that size and speed cannot be optimized simultaneously.

Superconducting packet switch

Very broad band throughputs greater than 1T bit/sec are desired in heavily loaded communication systems. Using the merits of superconducting devices, a superconducting network system is expected to improve the throughputs of such communication bottleneck systems. The paper describes a superconducting packet switch which is indispensable to a proposed superconducting network system. Considering the characteristics of various switch architectures, the space-division Banyan type architecture is adopted for a superconducting packet switch proto-type. The complete design of the proto-type is performed and the total operation is numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is a key component of the proto-type. The basic switching element with one-bit data width is fabricated and the correct operation is completely confirmed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Rearrangeable nonblocking Log/sub 2d/ (N, m, p) networks

Previously, a new class of switching networks, called Log/sub 2/ (N, m, p) networks, has been created for high-speed switching systems. The basic switching element used is a 2/spl times/2 crossbar. Although it is generally true that different sizes of switching elements can be used as the basic building block for the same design paradigm, the results are quite different. The sizes of the basic building block are often a trade-off among many factors such as combinatorial power, computation time of routing, fault tolerance, hardware complexity, and growth rate of a network. The authors study the design principle for Log/sub 2d/ (N, m, p) systems in this paper where d/spl ges/1. >

Biochemical switching device: biomimetic approach and application to neural network study

There are many examples of enzymes that share substrates or cofactors in a cyclic manner. Techniques have been developed that use cyclic enzyme systems to assay quantitatively small amounts of biochemical substances (cofactor, substrate), however, only a few studies of the control of these systems have been published. The author previously showed with computer simulations that cyclic enzyme systems have the reliability of on-off types of operation (McCulloch-Pitts' neuronic equation) capable of storing short-memory, and the applicability for a switching circuit in a biocomputer. This paper introduces a unique switching mechanism of cyclic enzyme system (basic switching element), and next, building the integrated biochemical switching system being composed of the basic switching element, shows the physiological phenomenon termed ‘selective elimination of synapses’ generally produced as a result of low-frequency train of electrical stimuli to the synapses (Kuroda, Y. (1989) Neurochem. Int. 14, 309–319).

Decomposition of output queuing switches

A large switch is often constructed with multiple stages of switching elements to reduce the hardware complexity or the speedup. Multiple-stage structures allow either blocking or nonblocking configurations. The blocking configuration suffers from the congestion of packets in a part of the switch. The nonblocking configuration requires a centralised control to route the packets through the switch. A centralised control creates a bottleneck when the switch operates at a high data rate. The paper introduces a simple technique to reduce the complexity of the output queuing switch with a speedup without either losing the self-routing characteristic or allowing performance degradation under nonuniform traffic patterns. Any of the output queuing switches with a speedup can be used as a basic switching element. The switching elements are then interconnected with the distributors in multiple stages. By introducing the distributors between stages of switching elements, the packets can be evenly distributed to all the input ports of the switching elements in the following stages. Although the switch becomes blocking, it retains the self-routing property and achieves the maximum throughput of 100% with only a small additional delay.

A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture

The paper describes a multistage shuffle interconnection network which is controlled by a central monitor. A control code broadcast by the monitor to all the basic switching elements of the network simultaneously, makes the network dynamically reconfigurable. The control code plays three vital roles. Firstly, it establishes conflict-free paths between several source-destination pairs. Thus the problem of collision, a major obstacle of a self-routing network, is completely eliminated. Secondly, the direct paths are established in one clock period irrespective of the number of stages. This makes the system faster. Thirdly, the control code also acts as a grouping code for executing a table of arbitrary data exchange requests between nodes in minimum number of passes. It is also shown that the network can be made fault-tolerant by the addition of an extra stage. Any single fault and some multiple faults in the intermediate stages can be tolerated by this scheme. Moreover, the switching from the faulty state to the fault-free state can be done in a single clock period, thus enabling fast fault-tolerant reconfiguration.

On permutations passable by the gamma network

The Gamma network is a multiprocessor interconnection network with redundant paths between source and destination terminals. The basic switching element in this network is a 3 × 3 crossbar, and the stages are linked by “power of two” and identity connections. The Gamma network is known to realize many classes of permutations useful in parallel processing, and in this paper a detailed study of various classes of permutations passable by the network with a simple control algorithm is presented. Conditions for passability of an arbitrary permutation with this algorithm have been formulated and used to show that several useful classes of permutations in parallel processing can be realized. Although the algorithm does not utilize the full connection capability of the network, it produces conflict-free routing for most of the useful classes of permutations the network is capable of passing.

Sorting and Rearrangeable Switching Networks

Some rearrangeable switching networks are developed by considering some familiar sorting procedures. The basic switching element in these networks is a two-state device (essentially a doublepole double-throw (DPDT) switch) that can be controlled by a comparator circuit in most cases. The complexity of the networks is discussed in terms of the number of these two-state devices and the number of stages m which these devices can be operated in parallel. Networks having more input ports than output ports are also considered.

Logical operations by interferometric techniques

A set of basic switching elements for performing logical operations on optical signals is considered. The devices are based on interferometric techniques associated with changes in optical paths introduced by electro-optical cells. It is shown that the most general switching function can be implemented without making recourse to any intermediate optical-to-electrical signal conversion.

An integrated FET analog switch

The use of a field-effect transistor as the basic switching element permits the design of integrated analog switches with extremely low offset-voltage and good isolation from ground. The static behavior of an FET as an analog switch is described by its on-impedance and its off-leakage current. The switching speed is limited by capacitive coupling between the gate and the channel of the FET. A figure of merit for chopper FET's relates the resulting transients on the signal line to basic design parameters. Design considerations for a driving circuit are presented. The use of such advanced techniques as multiple epitaxial deposition leads to a monolithic structure which optimizes the field-effect transistor as well as the elements of the driving circuitry. The resulting device, integrated on a 0.06-inch×0.06-inch silicon chip, compares favorably with conventional analog switches.

Precision Continuous Current Integrator

An all-electronic precision current integrator for use with a charged particle accelerator has been developed which eliminates the substantial deadtime normally associated with multicycle current integrators utilizing relays as their basic switching elements. Integration is accomplished in the conventional fashion of charging a precision condenser with the current to be integrated, electronically noting the completion of a predetermined voltage excursion and then returning the condenser to its initial charge state for repetition of the cycle. A unique feature of this integrator is the return of the integrating condenser to its initial charge state through the transfer of a precise amount of negative charge to the condenser by an all-electronic charge transfer circuit. Integration continues during the charge transfer with no interruption and with no effect on the precision of integration. An electronic counter circuit interrupts the integration at the end of a preset number of cycles and gates off any associated equipment. Current range is approximately 1–500 μa. Accuracy at low currents is limited primarily by a total circuit leakage current of the order of 1.5×10−9 amp. At higher currents, electrometer and other circuit instabilities limit accuracy to slightly better than 0.01%.