Banyan Switch Research Articles

Analysis and design of Banyan and crossbar switches with bypass queues

Bypass queueing can overcome the problem of head of line blocking within an input queue. We study two different approaches for providing a bypass function in input buffers. They are look-through and look-back service disciplines, both of which can prevent out of sequence situations. Under uniform traffic, if the switch size is large, these two disciplines obtain almost the same throughput. However, under nonuniform traffic, especially a hot-spot traffic pattern, the look-through will achieve a much better throughput than look-back policy. This paper presents the throughput analysis and simulations for crossbar and Banyan switches under uniform and nonuniform traffic. Furthermore, to reduce contention across input queues, the parallel-plane ATM switch with bypass queues is also discussed and analyzed.

A 4 X 4 superconducting Batcher-Banyan switch

The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks. The Batcher sorter is composed of 2/spl times/2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4/spl times/4 Batcher sorter with 2-b data width, which is composed of six 2/spl times/2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed. The Banyan network consists of 2/spl times/2 Banyan switching elements. A 2/spl times/2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.

Performance Analysis of Tandem Banyan Fast Packet Switch

The most appropriate switching technique for Broadband Integrated services Digital Networks (B-ISDN) is emerging to be packet switching. It offers greater flexibility over circuit switching in handling wide range of data rates and latency requirements resulting from integration of services. The real challenge lies in the design of switch that can be capable of switching 100000 packets/sec/line to 1000000 packets/sec/line, each packet of 424 bits.In this paper a space division fast packet switch based on banyan interconnection networks, called “tandem banyan switching fabric” is discussed. It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming the problem of blocking encountered in banyan networks and achieving output buffering. The beauty of banyan networks is its modularity and small input line switch can be building block for a large switch. Here “Omega” type banyan network is used for evaluation of the performance of the switch.Using computer simulation the switch performance is analyzed under different input traffic patterns and the effect of recirculation buffers also studied.

Admission control for variable bit rate video in Banyan switches

When a Banyan switch is used to switch variable bit rate (VBR) video, some video packets may not be switched before their deadlines because the VBR video sources may temporarily generate heavy traffic or they only generate moderate traffic but some video packets encounter internal blocking in the switch. Therefore, some video packets may be discarded. We determine the condition of packet loss and then derive the packet loss probability. Based on this result, we perform admission control to determine whether a given video session can be admitted while the resulting packet loss probability is still small enough to guarantee a good image quality.

Architecture and Performance Comparison of High‐speed Switch Networks

AbstractThis paper evaluates and analyzes performance of the growable switch, bypass queue switch, and tandem banyan switch in ATM networks.

On a class of Banyan networks and tandem Banyan switching fabrics

This paper examines the operating characteristics of a class of tandem Banyan switching fabrics (TBSF's) built using bi-delta networks. We use the functional equivalence between bi-delta networks to induce an equivalence between TBSF's. A weaker form of equivalence guaranteeing identical performance under conditions of symmetric traffic is studied, and a sufficient condition for weak equivalence between functionally distinct TBSF's is established. These results hold for a variety of conflict resolution policies (CRP's) in addition to the one studied by Tobagi et al. (see IEEE J. Select. Areas Commun., vol.9, p.1173, 1991). Simulations indicate that a TBSF constructed by cascading omega networks, (or in fact any other TBSF in its weak equivalence class), performs better than the two TBSF's studied by Tobagi et al., and converges rapidly to a theoretical lower bound on the loss rate, in the region of interest. It is also shown that this loss rate is almost independent of the size of such a TBSF in the region of interest.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance modelling of a multi-buffered banyan switch under bursty traffic

Presents an approximation algorithm for the analysis of a buffered banyan ATM switch which allows complex (input and output buffering) switching elements, bursty traffic, non-uniform destination distribution and permits the analysis of large scale switches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Throughput analysis and optimal design of Banyan switches with bypass queues

A Banyan switch with bypass queue can overcome the problem of head of line blocking. This paper presents the throughput analysis for such a switch and the optimal window size for the bypass queue is also obtained. Moreover, to reduce the effect of the internal blocking and to increase the throughput, a parallel Banyan switch with bypass queue is also discussed and analyzed. >

A high‐speed‐retry banyan switch architecture for giga‐bit‐rate BISDN networks

AbstractThis paper proposes a high‐speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross‐connect system. The proposed switch architecture, named the high‐speed‐retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell‐retransmission algorithm, is employed as is a ring‐arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high‐speed‐retry banyan switch. The prototype system, even in its present state, could be used to realize a giga‐bit‐rate BISDN switching system.

Performance analysis of nonblocking packet switch with input and output buffers

The performance of nonblocking packet switches such as the knockout switch and Batcher banyan switch for high-speed communication networks can be improved as the switching capacity L per output increases; the switching capacity per output refers to the maximum number of packets transferred to an output during a slot. The N*N switch with L=N was shown to attain the best possible performance by M.J. Karol et al. (1987). Here a N*N nonblocking packet switch with input and output buffers is analyzed for an arbitrary number of L such that 1 >

Design of a folded banyan switching network with by-pass links using a distribution cell sequence control

The asynchronous transfer mode (ATM) is considered to be important as a key technology in realizing a broadband ISDN that can handle diversified services in a unified way. The high-speed burst multiple transmission system using ATM is proposed. This paper considers the folded Banyan network with by-pass links which is proposed as a cross-connect switch to be applied to the cross-connect MUX of the high-speed burst multiple transmission system. A routing method that preserves the time sequence of cells also is proposed and its cell transfer performance is analyzed. The proposed routing method is realized by a distributed control. It is shown that the method can be applied at the same time preserving the features of the folded Banyan network with by-pass links, which are the unified modularity and the expansion without interruption. For the performance evaluation, a method of analysis is presented which improves the approximation of the traditional analysis of the cell loss rate.

Performance of a 2 × 2 banyan switch with non-symmetric traffic and variable message lengths

Banyan networks are being proposed as switching elements in Broadband ISDN. The 2 × 2 crossbar switch is the building block of the Banyan networks. This paper describes an analysis of the performance of a finite buffered 2 × 2 switch, based on a Markov chain where the points immediately following arrivals and departures to and from the switch are chosen as the embedded points. These embedded points provide a manageable state space. The use of non-homogenous embedded points causes difficulties, and it requires a rather involved transformation to determine the steady state distribution of the number of messages in the buffers. Results include steady state probability distribution of the number of messages in the buffers, average delay and blocking probability for symmetric and non-symmetric arrivals, and variable length messages into the switch. These results are significant in Broadband ISDN for variable length messages 1,2.

Tandem banyan switching fabric with dilation

The recently proposed fast packet switch for BISDN, called the tandem banyan switching fabric, achieves the performance of an output-buffered switch. To attain a low packet loss rate, however, it may be necessary to use many banyan networks connected in series. In the Letter it is shown that the number of banyan networks can be substantially reduced by using dilated banyans to attain the same performance.

Architecture, performance, and implementation of the tandem banyan fast packet switch

The authors propose a new space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric (TBSF). It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8- mu m technology is reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The dilated slipped Banyan switching network architecture for use in an all-optical local-area network

A modification of the classical banyan switching network architecture, called the dilated slipped banyan, is described. This architecture is recursive and switching networks of any size perform permutation switching under a simple switching rule. They also exhibit column-control and dilation, properties that are particularly relevant to guided-wave and free-space photonic technologies. A photonic switching network, with this dilated slipped banyan architecture, is proposed as the hub of an all-optical active-star local-area network. The switching assignment at this hub is time-multiplexed on a fixed schedule that is known to all the terminals. This all-optical local-area network provides the equivalent of full-connectivity with high simultaneous data rates between every pair of terminals. A 16-terminal local-area network with 100 Mb/s of contention-free bandwidth between every pair of terminals is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Atm cross‐connect switch using folded banyan switching network with bypass links

AbstractA high‐speed multiplex transmission system has recently been proposed based on ATM, where the information is divided into fixed‐length blocks called cells, and transmitted on asynchronous multiplexing basis. As the switch to be used in the transit node in such a transmission system, various kinds of switching networks have been proposed, composed of two‐input × two‐output switch elements with internal buffers. Among those, the multistage buffered Banyan structure, which is a cascade connection of two Banyan networks as the distribution and routing networks, is of a distributed structure, being suited to LSI implementation. The network is a promising candidate since it realizes the self‐routing and is stable against a variety of traffic. However, this switching network has a problem in that the delay is increased with the scale of the network, and the in‐service expansion of the switching network is not easy.This paper proposes a new network topology of the Banyan network with bypass links, together with the self‐routing method, and describes its performance. The network is composed of the distribution and routing networks with bypass links between individual unit switches. By transferring cells from the distribution network to the routing network through the bypass links at appropriate stages, the delay is reduced. The in‐service expansion of the system is made easy.

Architecture of a packet switch based on banyan switching network with feedback loops

The authors propose and describe an original feedback banyan switching network topology and control algorithm. This feedback banyan network prevents congestion even at high throughput. It does so by establishing a feedback route for the output packets from the output port to the input port of the banyan switching network. Input accommodated logical channels that do not encounter congestion within the switching network are output directly from the intended output port. Other packets are returned to the input port via the feedback route, then rerouted. >